Multiple Gate Semiconductor Devices for Parasitic Resistance Reduction
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Solution Overview
Problem
Conventional FinFETs exhibit higher parasitic resistance due to their narrow fin structure, which reduces the quality factor (Q) of varactors and is not area efficient, especially when connecting a tuning voltage, requiring large series resistance that blocks AC signals and consumes valuable device area.
Innovation Solution
A multiple gate semiconductor device with a fin structure having first and second major surfaces, each with a gate, and differential inputs, allowing a virtual ground to be established when voltages of opposite polarity are applied, enabling a tuning voltage to be coupled without external resistance, thus reducing parasitic resistance and improving area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional FinFET structure is used, then device scaling to 20nm and smaller is achieved, but parasitic resistance increases significantly
Solution Approach 1:
The fin structure is segmented into multiple fins (e.g., four fins) with gates on opposite surfaces, allowing the capacitor to be formed by connecting sources/drains of some fins to one plate and gates to the other plate. This segmentation enables achieving the desired capacitance with reduced parasitic resistance by distributing the current paths across multiple parallel channels.
Solution Approach 2:
The invention utilizes the third dimension by forming gates on both the top and bottom surfaces of the fin structure, effectively using the vertical dimension to create additional gate surfaces. This multi-surface gate configuration increases the effective gate area without increasing the planar footprint, thereby reducing parasitic resistance while maintaining compact device scaling.
2Reliability
If FinFET with two independent gates is used, then quality factor is improved by eliminating parasitic source drain resistance, but area efficiency decreases requiring four times as many fins
Solution Approach 1:
The invention merges the functionality of multiple fins into a single integrated structure where sources and drains of multiple fins are connected together to form capacitor plates. By combining multiple fins and their gates into one unified capacitor device, the invention achieves the desired capacitance and quality factor without requiring four times the area, as the merged structure utilizes shared source/drain regions and common gate connections.
3Object-affected harmful factors
If tuning voltage connection is made through large series resistance, then AC signal transmission is blocked, but valuable device area is consumed
Solution Approach 1:
The invention extracts the tuning voltage connection from the conventional approach that requires large series resistance by directly coupling the tuning voltage to the fin structure. The virtual ground configuration allows the tuning voltage to be applied without needing external series resistance, thereby eliminating the area consumption associated with large resistance elements while maintaining effective AC signal blocking through the virtual ground mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the quality factor of varactors and other circuit applications by eliminating the need for external resistance to block AC signals, while maintaining area efficiency and allowing for effective tuning voltage application.
Implementation Method 1
A voltage applied to the gate controls current flow in an un-doped channel that extends between the doped source and drain regions in the semiconductor beneath the gate
Implementation Method 2
The gate is insulated from the semiconductor by a thin layer of an insulator such as silicon oxide
Implementation Method 3
the source and drain serve as one plate of the capacitor and the gate serves as the other plate with the two plates being separated by the gate insulator
Data Source
AI summary
A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.