Multiple-Gate Pseudo-Inverter Wordline Driver for Compact DRAM Access

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Solution Overview

Problem

Conventional wordline driver circuits for DRAM memory cells are bulky and consume significant area and power, leading to integration challenges and high power consumption, especially when addressing multiple memory cells.

Innovation Solution

A pseudo-inverter circuit using multiple gate transistors with independent control gates, configured to operate in depletion mode, is designed on a semiconductor-on-insulator substrate, allowing for reduced size and power consumption by providing logic INV, NOR, and NAND functions, and is used in a wordline driver circuit for memory arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stress or pressure

If conventional wordline driver circuits are used, then high voltage can be delivered to memory cells, but the circuit area becomes large and integration becomes difficult

Engineering Contradiction:

Improvevoltage delivery capabilityVSAvoidcircuit area

Core Design Contradiction:

Stress or pressureVSArea of stationary object

Solution Approach 1:

The patent merges multiple driver circuits into a single integrated structure by stacking them vertically on the same substrate. The first driver circuit and second driver circuit share the same physical space through vertical integration, allowing high voltage delivery to multiple memory cell lines simultaneously while minimizing the horizontal circuit area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from horizontal layout to vertical stacking by positioning driver circuits at different heights (first substrate and second substrate) along the vertical dimension. This allows multiple driver circuits to coexist in the same footprint area by utilizing the third dimension (height), thereby reducing the overall circuit area while maintaining voltage delivery capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If conventional wordline driver circuits are used, then memory cells can be accessed, but power consumption becomes significant

Engineering Contradiction:

Improvememory cell access capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent employs periodic switching of the driver circuits where only the active driver circuit consumes significant power at any given time. The first driver circuit and second driver circuit are activated alternately based on memory access patterns, allowing inactive circuits to enter low-power states. This periodic activation reduces overall power consumption while maintaining reliable memory cell access capability.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9496877B2Pseudo-inverter circuit with multiple independent gate transistors

Publication Date: 2016.11.15 SOITEC SA

AI summary

The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).