Multiple-Height Cell Transistor Layout for Reduced Local Layout Effects
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Solution Overview
Problem
Integrated circuits face challenges in reducing local layout effects (LLE) between cells, which can impact transistor performance and operating speed, and existing solutions do not effectively enhance the number of transistors adjacent to diffusion breaks for improved characteristics.
Innovation Solution
The integration of multiple height cells with active regions terminated by diffusion breaks, specifically double diffusion breaks for improved transistor performance, allows for a higher number of transistors adjacent to these breaks, enhancing operating speed and reducing LLE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple height cells are used to increase the number of transistors adjacent to diffusion breaks, then transistor performance and operating speed are improved, but cell structure complexity increases
Solution Approach 1:
The cell is divided into multiple height segments (first height and second height) with different numbers of transistor groups. This segmentation allows each segment to be optimized independently - the first height cell contains a first number of transistor groups while the second height cell contains a second number of transistor groups, enabling increased total transistors adjacent to diffusion breaks without creating a single overly complex cell structure
Solution Approach 2:
The patent extends the cell structure in the vertical dimension by creating multiple height cells stacked or arranged in sequence. Instead of expanding horizontally with more transistors in a single layer, the solution uses vertical stacking of transistor groups across different height levels, thereby increasing the number of transistors adjacent to diffusion breaks while maintaining manageable complexity in each individual cell layer
2Reliability
If diffusion breaks are added to terminate active regions, then local layout effects are reduced and transistor characteristics are improved, but manufacturing process complexity increases
Solution Approach 1:
Diffusion breaks are pre-positioned at predetermined locations where active regions are to be terminated. By planning the diffusion break locations in advance during the cell design phase - specifically at boundaries between transistor groups and at active region endings - the manufacturing process follows a clear, predetermined pattern rather than requiring complex real-time decisions, thereby reducing manufacturing complexity while still achieving the benefit of reduced local layout effects
3Power
If transistor groups are arranged in parallel to increase driving strength, then operating speed is improved, but area occupancy increases
Solution Approach 1:
Transistor groups are arranged in parallel across multiple vertical layers (first height and second height) rather than spreading them out horizontally in a single layer. This vertical stacking approach increases the effective area utilization, allowing more transistor groups to share the same horizontal footprint by distributing them across different height levels, thereby increasing driving strength without proportionally increasing the overall cell area
Data Source
AI summary
Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.