Multiple Main Spine Routing for IC Net Length Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CAD routing methods for integrated circuits face challenges in efficiently routing nets with multiple pins across constrained layout planes, particularly when blockages and limited routing tracks restrict the use of single main spine wires, leading to longer net lengths and increased parasitic capacitance and resistance.
Innovation Solution
The method involves selecting multiple main spine routing tracks and generating multiple main spine wires, both horizontally and vertically, to connect pin groups, thereby reducing net length and improving routing flexibility and efficiency by partitioning pins into groups associated with specific tracks and using cost functions to optimize wire placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single main spine wire is used to route nets, then the routing structure is simple, but the net length increases and parasitic capacitance and resistance increase
Solution Approach 1:
The patent divides a single main spine wire into multiple separate main spine wires to route different groups of pins. This segmentation allows each spine wire to serve a specific pin group, reducing the overall net length and associated parasitic effects while maintaining manageable routing complexity.
Solution Approach 2:
The patent introduces a hierarchical dimension to routing by creating multiple levels of spine wires (first level main spines, second level main spines, and branch spines). This multi-level structure enables more efficient path planning through the layout, reducing net length without proportionally increasing routing complexity.
2Object-affected harmful factors
If multiple main spine wires are used to reduce net length, then parasitic capacitance and resistance decrease, but routing complexity increases
Solution Approach 1:
The routing problem is segmented by dividing pins into distinct groups, each assigned to a specific main spine wire. This segmentation strategy reduces net length for each group while keeping the number of spine wires manageable, thus controlling routing complexity.
Solution Approach 2:
Different regions of the layout are assigned different routing characteristics by creating localized main spine wires for specific pin groups. This allows optimization of net length in high-density regions while avoiding unnecessary complexity in lower-density regions.
3Adaptability or versatility
If routing tracks are constrained by blockages, then layout flexibility is reduced, but net length increases
Solution Approach 1:
The patent creates a multi-level routing hierarchy with first level main spines, second level main spines, and branch spines. This vertical dimension allows routing paths to bypass blockages by moving between levels, maintaining routing flexibility while reducing net length compared to single-level alternatives.
Solution Approach 2:
Branch spines act as intermediary connections between first level main spines and second level main spines. These intermediaries provide flexible routing paths around blockages, allowing the network to adapt to layout constraints while minimizing net length.
4Productivity
If pins are partitioned into groups and assigned to specific tracks, then routing efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the set of pins into multiple groups, with each group assigned to a specific main spine wire and routing track. This segmentation enables systematic and efficient routing by handling pin groups independently, improving routing productivity while keeping the complexity of each individual routing path manageable.
Solution Approach 2:
The multi-level spine structure serves multiple functions: first level main spines provide primary routing, second level main spines provide alternative paths and connections, and branch spines connect the two levels. This multi-functional hierarchy improves routing efficiency for different pin configurations without requiring completely different routing structures for each case.
Data Source
AI summary
A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.