Multiple Mask Patterning for Sub-Wavelength IC Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As technology advances, the gap between the wavelength of light used in photolithography and the minimum feature size of integrated circuits widens, making it costly to achieve sub-wavelength resolution in integrated circuit fabrication, especially at smaller technology nodes, where complex resolution enhancement techniques are required.
Innovation Solution
The use of multiple masks and multiple masking layers allows for superior fidelity in patterning a single integrated circuit layer, with the first mask defining sub-wavelength fine-line patterns and subsequent masks used to connect these features and define coarse features, reducing the need for costly resolution enhancement techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex resolution enhancement techniques are used to achieve sub-wavelength resolution, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps using multiple masks and masking layers. Instead of relying on a single complex resolution enhancement technique, the process segments the pattern formation into: (1) forming mandrels at relaxed pitch, (2) depositing spacers conformally on mandrels, (3) selectively removing mandrels, and (4) repeating the process. This segmentation achieves sub-wavelength resolution through simple geometric constraints rather than complex optical or chemical techniques.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical patterning by utilizing the thickness dimension of conformally deposited spacer layers. The critical dimension of the final pattern is determined by the spacer thickness rather than the lithographic resolution, effectively using the vertical dimension to achieve sub-wavelength features that would be impossible to form directly in the lateral dimension with available lithography tools.
2Manufacturing precision
If multiple masks and masking layers are used to pattern a single IC layer, then manufacturing precision is improved, but the number of process steps increases
Solution Approach 1:
The patent combines multiple patterning functions into a unified self-aligned process. The spacer deposition step simultaneously serves as both a pattern definition step and an alignment reference for subsequent steps. The conformal deposition process inherently aligns the spacer pattern to the mandrel pattern without requiring additional alignment steps, merging pattern formation and alignment into a single operation that reduces the total number of process steps despite using multiple masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective sub-wavelength feature definition by leveraging multiple masks and masking layers to minimize the use of expensive resolution enhancement techniques, thereby lowering the cost per IC design and maintaining high pattern fidelity.
Implementation Method 1
a first mask is used to define one or more geometrically regular fine-line patterns in a first masking layer on a surface of a wafer
Implementation Method 2
selected portions of the fine-line patterns can then be removed using a second mask
Data Source
AI summary
A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.