Multiple-Memory DSP Architecture for High-Speed Signal Processing
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Solution Overview
Problem
Current digital signal processors (DSPs) face limitations in achieving higher performance and speed while maintaining precision and accuracy, particularly in high-performance computing applications, where they often fall short of providing the necessary processing capabilities.
Innovation Solution
The development of an integrated circuit device featuring an Application-Specific Digital Signal Processor (ASDSP) with multiple memory banks, comprising a control unit, data unit, and function core, which is optimized for specific mathematical expressions and algorithms, allowing for efficient data processing and execution of digital signal processing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional digital signal processors are used, then basic processing capabilities are provided, but higher performance and speed cannot be achieved
Solution Approach 1:
The processor is divided into multiple independent memory banks (first memory bank, second memory bank, third memory bank) that can operate simultaneously. Each memory bank handles specific data streams, allowing parallel access and eliminating memory bottlenecks, thereby achieving higher processing speed without proportionally increasing overall system complexity
Solution Approach 2:
The patent introduces a multi-dimensional memory architecture where data can be accessed from multiple memory banks simultaneously along different data paths. This dimensional expansion of memory access allows the processor to handle complex algorithms with multiple data streams in parallel, improving productivity while maintaining manageable complexity through structured organization
2Speed
If processing speed is increased, then computational bottlenecks are reduced, but maintaining precision and accuracy becomes more difficult
Solution Approach 1:
Complex computational tasks are segmented and distributed across multiple function cores, each specialized for specific algorithmic operations. This segmentation allows each core to maintain precise computational logic for its designated function while the overall system achieves high speed through parallel execution of multiple segmented tasks
Solution Approach 2:
The control unit acts as an intermediary that coordinates data flow between multiple memory banks and function cores, ensuring that precision-critical operations are executed in the correct sequence and that data integrity is maintained throughout the high-speed processing pipeline
3Productivity
If multiple memory banks are integrated, then data access efficiency is improved, but device complexity increases
Solution Approach 1:
The memory system is segmented into multiple independent banks, each capable of simultaneous access. This segmentation improves data access efficiency by allowing parallel reads/writes from different memory banks, while the modular nature of each bank keeps individual unit complexity manageable
Solution Approach 2:
Each memory bank is designed with universal interfaces and control logic that can handle various data types and access patterns. This multi-functionality reduces the need for specialized complex control circuits for each bank, thereby improving data access efficiency while limiting the increase in overall device complexity
Data Source
AI summary
An integrated circuit device is provided comprising a circuit board and one or more digital signal processors implemented thereon. The digital signal processor comprises a data unit comprising a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application and an instruction memory storing one or more instructions configured to send commands to the control unit and the data unit to perform the specific application, and a control unit configured to control the flow of data between a plurality of memory banks and the function core for performing the specific application, and the plurality of memory banks coupled to each of the one or more digital signal processors and comprising at least two or more local memory banks integrated onto the circuit board.