Multiple-NAND Storage With Phased Program-Erase Scheduling
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Solution Overview
Problem
The consistency of write performance in storage devices with multiple NAND dies is compromised due to the need for simultaneous erase operations, leading to periods where no programming can occur, resulting in zero throughput during erase cycles.
Innovation Solution
Implementing a memory controller that manages NAND dies in super blocks, completing programming and erase operations in phases, and allowing partial overlap of erase operations to minimize throughput disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all NAND dies are managed with strict super block management requiring complete erase before programming, then data integrity is improved, but write throughput drops to zero during erase cycles
Solution Approach 1:
The patent segments the erase operation into multiple phases (first phase erase and second phase erase) that can be interleaved with programming operations on different dies. This allows the erase operation to be divided such that while one die undergoes first phase erase, another die can be programmed, and subsequently the second phase erase is performed, thereby maintaining data integrity while preventing write throughput from dropping to zero.
Solution Approach 2:
The patent performs a first phase erase operation on a die before programming another die, preparing the erase state in advance. This preliminary action allows the system to maintain a pipeline where erase and program operations are staggered across multiple dies, ensuring that when one die needs to be programmed, another die is already in a ready state, thus maintaining continuous write throughput while preserving data integrity through complete erase before program.
2Stability of the object's composition
If multiple NAND dies are operated in parallel with simultaneous erase operations, then write performance consistency is improved, but buffer memory requirements increase significantly
Solution Approach 1:
The patent segments the buffer memory usage by implementing separate queues for different operation phases (first phase erase queue, second phase erase queue, program queue). This segmentation allows the system to manage buffer memory in smaller, phase-specific allocations rather than requiring a large unified buffer, while still maintaining parallel operation of multiple dies to ensure write performance consistency.
Solution Approach 2:
The patent implements periodic switching between different operation phases across multiple dies. Instead of requiring all dies to be in the same operation state simultaneously (which would demand large buffer memory), the system periodically rotates through different phase combinations, allowing buffer memory to be reused across phases while maintaining consistent write performance through the parallel periodic operations.
Data Source
AI summary
A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.