Multiple Page Tables for Heterogeneous Processor Function Pointers
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Solution Overview
Problem
Heterogeneous computing systems face challenges in supporting function pointers across processors with different instruction set architectures, leading to errors when executing functions written for one ISA on another.
Innovation Solution
The implementation of a heterogeneous execution system using multiple page tables to translate virtual memory addresses into physical addresses, allowing a single virtual memory address to point to executable code that can be executed by processors with different ISAs, thereby supporting function pointers and enabling seamless execution across processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single virtual memory address is used to point to a function, then function pointers can be passed between threads, but the system cannot support heterogeneous processors with different ISAs executing the same function pointer
Solution Approach 1:
The patent segments the page table into multiple distinct page tables (first page table, second page table, etc.), each associated with a specific processor or ISA type. This segmentation allows each page table to independently map virtual addresses to physical addresses appropriate for its target architecture, resolving the contradiction by enabling a single virtual address to be correctly interpreted across heterogeneous processors.
Solution Approach 2:
The patent introduces the virtual memory manager as an intermediary that selects which page table to use based on the target processor's ISA type. This intermediary layer translates the function pointer (virtual address) appropriately for each processor type, allowing function pointers to be universally passed while maintaining execution correctness for each specific architecture.
2Reliability
If multiple page tables are implemented to support heterogeneous processors, then function pointers can be correctly resolved for different ISAs, but the system complexity increases
Solution Approach 1:
The patent makes the virtual memory manager universal by giving it the capability to work with multiple different page tables and select the appropriate one based on the target processor type. This multi-functionality allows a single virtual memory manager implementation to handle heterogeneous processors without requiring separate memory management systems for each ISA, thus reducing overall system complexity while maintaining execution correctness.
Solution Approach 2:
The patent introduces dynamic selection of page tables based on the target processor's ISA type. The virtual memory manager dynamically determines which page table to use at runtime based on the function pointer's target architecture, allowing the system to adapt to different processor types without static configuration or hardcoding for each ISA.
3Device complexity
If traditional single page table systems are used, then memory management is simple, but function pointers cannot be reliably passed between threads on heterogeneous processors
Solution Approach 1:
The patent segments the traditional single page table into multiple processor-specific page tables, each handling a specific ISA type. This segmentation enables cross-processor function pointer support by ensuring that each processor type has its own mapping rules, while the virtual memory manager coordinates between them to maintain overall system simplicity.
Solution Approach 2:
The virtual memory manager acts as an intermediary that shields the complexity of multiple page tables from the rest of the system. It provides a unified interface for function pointer passing while internally managing the complexity of selecting and coordinating between multiple page tables, thus maintaining simplicity for application code despite the underlying complexity.
Data Source
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AI summary
Embodiments of techniques and systems for execution of code with multiple page tables are described. In embodiments, a heterogenous system utilizing multiple processors may use multiple page tables to selectively execute appropriate ones of different versions of executable code. The system may be configured to support use of function pointers to virtual memory addresses. In embodiments, a virtual memory address may be mapped, such as during a code fetch, in embodiments, when a processor seeks to perform a code fetch using the function pointer, a page table associated with the processor may be used to translate the virtual memory address to a physical memory address where code executable by the processor may be found. Usage of multiple page tables may allow the system to support function pointers while utilizing only one virtual memory address for each function that is pointed to. Other embodiments may be described and claimed.