Multiple pBIST Controllers for Parallel SoC Testing
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Solution Overview
Problem
Testing complex integrated circuits becomes increasingly difficult due to their complexity, necessitating efficient methods for detecting design and manufacturing defects before large-scale production and shipment.
Innovation Solution
A system on a single integrated circuit chip (SoC) with multiple programmable built-in self-test (pBIST) controllers connected to operational circuits, allowing parallel testing and reporting of results to an external tester, facilitated by an interface for programming and utilizing a VLCT protocol for efficient register programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple pBIST controllers are used to test multiple operational circuits in parallel, then test time is reduced and productivity is improved, but device complexity increases
Solution Approach 1:
The system divides the testing function into multiple independent pBIST controllers, each responsible for testing specific operational circuits. This segmentation allows parallel testing of different circuit blocks simultaneously, reducing overall test time while maintaining manageable complexity through modular organization
Solution Approach 2:
Multiple pBIST controllers share common resources including a single VLCT interface for programming, shared ROM for test instructions, and common reporting mechanisms. This multi-functionality approach allows the same hardware resources to serve multiple controllers, improving productivity without proportionally increasing device complexity
2Ease of operation
If a VLCT interface is implemented for programming pBIST controllers, then ease of operation is improved and programming efficiency is enhanced, but device complexity increases
Solution Approach 1:
The VLCT interface enables self-programming capability where the pBIST controllers can be configured directly by external testers without requiring complex pre-programming tools. The interface allows external testers to load test instructions from ROM and program controller registers straightforwardly, improving ease of operation while keeping the interface itself relatively simple
Data Source
AI summary
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time.