Multiple-Port SRAM Layout with Back-Side Routing for GAA Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits (ICs) continue to scale down, interconnection routing for memory cells using gate-all-around (GAA) transistors becomes complex, consuming too many routing resources and impacting cell scaling and performance.
Innovation Solution
A compact multiple-port SRAM cell design with GAA transistors featuring both front-side and back-side metal conductors, reducing resistance and routing complexity by incorporating write bit-line and write bit-line-bar conductors under the SRAM cell, along with a layout that includes ten transistors and utilizes back-side interconnection structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional interconnection routing is used for GAA transistor memory cells, then routing connectivity is achieved, but routing complexity increases and consumes too many routing resources
Solution Approach 1:
The patent utilizes both front-side and back-side of the substrate for interconnection routing, transitioning from a single-plane (2D) routing approach to a multi-plane (3D) approach. This allows routing resources to be distributed across two dimensions, reducing the complexity and resource consumption on the front-side while maintaining necessary connectivity for GAA transistor memory cell operation
2Device complexity
If more routing resources are allocated to memory cells, then interconnection is achieved, but cell scaling is impacted
Solution Approach 1:
By implementing back-side interconnection structures, the patent moves routing resources from the lateral plane to the vertical dimension. This enables the memory cell footprint to be reduced since routing no longer needs to occupy extensive lateral space, thereby improving cell scaling while maintaining adequate routing resources through the addition of back-side conductors
3Ease of manufacture
If front-side interconnection only is used, then manufacturing is simplified, but resistance is high and performance is limited
Solution Approach 1:
The interconnection system is segmented into front-side and back-side components, with each serving specific routing functions. The back-side interconnection structures handle specific signal paths that benefit from reduced resistance, while the front-side maintains manufacturing simplicity. This segmentation allows performance-critical paths to be optimized without complicating the overall manufacturing process
Data Source
AI summary
A memory structure includes a static random-access memory (SRAM) cell having a cell boundary. The SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor, a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, a second write-port PG transistor, a first read-port PD transistor, a second read-port PD transistor, a first read-port PG transistor, and a second read-port PG transistor respectively including nanostructures that are vertically stacked from each other. The memory structure further includes a write bit-line conductor and a write bit-line-bar conductor in a first metal layer under the SRAM cell, wherein the write bit-line conductor is electrically connected to a source/drain feature of the first write-port pass-gate transistor and the write bit-line-bar conductor is electrically connected to a source/drain feature of the second write-port pass-gate transistor.