Multiple Precision Memory System Non-Contiguous Addressing
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Solution Overview
Problem
Existing systems face inefficiencies in managing and processing floating-point numbers with different precisions, leading to suboptimal use of memory bandwidth, power, and processor resources due to the need for multiple memory accesses for varying precision formats.
Innovation Solution
Implementing a method where floating-point numbers are stored and retrieved using non-contiguous memory addresses, with each portion of the number located at the same offset within access units or memory arrays, allowing for efficient access and storage across different precision formats by configuring memory devices to handle multiple precision levels through column offsets and precision configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If floating-point numbers are stored using contiguous memory addresses for each precision format, then memory access is simple and direct, but multiple separate memory accesses are required for different precision formats, increasing memory bandwidth consumption and processing cycles
Solution Approach 1:
The patent segments floating-point numbers by storing different precision formats (e.g., single-precision and double-precision) in separate memory regions with distinct address spaces. This segmentation allows the system to efficiently access only the required precision level without retrieving unnecessary data, thereby reducing memory bandwidth consumption and processing cycles while maintaining simple access patterns within each precision segment.
Solution Approach 2:
The patent introduces an additional dimension to memory addressing by implementing precision-specific address spaces rather than using a single contiguous address space. This dimensional change enables the system to differentiate between precision formats through the address structure itself, allowing simultaneous or selective access to multiple precision formats without requiring separate memory requests, thus improving processing efficiency.
2Reliability
If multiple separate memory accesses are used for different precision formats, then each access can be optimized for its specific format, but memory bandwidth and processor resources are consumed inefficiently
Solution Approach 1:
The patent creates a universal memory access mechanism that handles multiple precision formats through a unified address space configuration. The memory system is designed to interpret addresses differently based on the requested precision format, allowing a single access mechanism to serve multiple precision requirements. This multi-functionality maintains format-specific access accuracy while reducing the number of separate memory transactions required, thereby lowering bandwidth consumption and energy usage.
3Productivity
If memory devices are configured to handle multiple precision levels, then resource usage is optimized, but the complexity of memory configuration and management increases
Solution Approach 1:
The patent implements dynamic precision configuration where the memory system can adaptively switch between different precision formats based on computational requirements. The address translation and memory access logic dynamically adjust according to the active precision level, allowing the system to optimize resource utilization for different workloads without requiring complex static configuration. This dynamic approach manages complexity by using runtime adaptation rather than elaborate pre-configuration.
Data Source
AI summary
Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.