Multiple Queue Output Buffering in Graphics Raster Stage

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Solution Overview

Problem

Existing 3-D rendering architectures struggle to scale with increasingly complex graphics applications, leading to performance issues without incurring increased power consumption and reduced fabrication yield.

Innovation Solution

Implementing a method and system for multiple queue output buffering in the raster stage of a graphics processor, where graphics primitives are rasterized into tiles, and sub-portions with coverage are transferred to output queues for balanced per-clock cycle output, minimizing empty slots and optimizing GPU performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional unidirectional rasterization methods are used, then the rendering process is simple to implement, but the performance cannot scale to handle high-resolution displays (1920×1200 pixels or larger)

Engineering Contradiction:
Improverendering performanceVSAvoidrasterization process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the rasterization process into two levels: first-level rasterization that generates tiles, and second-level rasterization that processes sub-portions of tiles. This segmentation allows the system to handle high-resolution displays by processing smaller manageable units (sub-portions) rather than entire frames at once, thereby scaling performance without proportionally increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the traditional flat rasterization process by creating multiple levels of abstraction (tiles containing sub-portions containing pixels). This dimensional transformation enables parallel processing at different hierarchy levels, improving productivity while keeping individual processing units relatively simple.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If clock speed is increased to improve rendering performance, then processing speed increases, but power consumption and heat production increase

Engineering Contradiction:
Improverendering performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

By segmenting the rendering workload into tiles and sub-portions that can be processed in parallel at lower clock speeds, the system achieves high overall throughput without requiring each processing unit to operate at high power-consuming frequencies. The parallel processing of multiple sub-portions compensates for lower individual clock speeds.

Inventive Principle:
Principle #1Segmentation

3Productivity

If large numbers of parallel execution units are incorporated to improve rendering performance, then processing throughput increases, but integrated circuit die size increases and manufacturing yield decreases

Engineering Contradiction:
Improverendering performanceVSAvoidintegrated circuit die size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic allocation and sharing of execution units across multiple tiles and sub-portions. Rather than dedicating fixed execution units to each parallel stream, the system dynamically assigns available execution units to different sub-portions based on current workload, enabling high throughput with a smaller number of physical execution units.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Execution units are designed to be universal and multi-functional, capable of processing different sub-portions from different tiles across multiple frames. This universality allows a smaller number of execution units to handle a larger total workload by being reused across different processing contexts, reducing die size while maintaining high productivity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Productivity

If output queues are not balanced, then some queues may have empty slots reducing efficiency, but implementing complex balancing mechanisms increases system complexity

Engineering Contradiction:
Improveoutput efficiencyVSAvoidqueue management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the rasterization unit monitors the state of output queues and dynamically adjusts its processing behavior. When certain queues have empty slots, the system feedback-controls the allocation of sub-portions to balance the load, improving output efficiency without requiring complex centralized queue management infrastructure.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8085264B1Tile output using multiple queue output buffering in a raster stage
Publication Date: 2011.12.27 NVIDIA CORP
  • US8085264B1 patent drawing
  • US8085264B1 patent drawing
  • US8085264B1 patent drawing

AI summary

A method for multiple queue output buffering in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels related to the graphics primitive. Each tile is then rasterized to determine related sub-portions of each tile. The related sub-portions are transferred to a plurality of output queues. The related sub-portions are subsequently output on a per queue basis and on a per clock cycle basis.