Multiple-Ramp Single-Slope ADC for Faster Low-Power Conversion
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Solution Overview
Problem
Conventional single-slope ADCs are power inefficient due to their slow operation and high power consumption, primarily because they require numerous comparator decisions, and successive approximation ADCs are unattractive in massive-parallel systems due to the need for separate DACs for each channel to achieve uniform system response.
Innovation Solution
Implementing a multiple-ramp single-slope ADC architecture where multiple non-overlapping ramp signals cover sub-ranges of the input range, allowing for simultaneous comparison and reducing the time required to converge on the analog input signal, thereby minimizing power consumption without the need for separate DACs for each channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single-slope ADC is used, then the circuit structure is simple, but the operation speed is slow and power consumption is high
Solution Approach 1:
The input voltage range is divided into multiple non-overlapping sub-ranges, each covered by a dedicated ramp signal. This segmentation allows the comparator to quickly identify which sub-range the input signal falls into, significantly reducing the comparison time and increasing operation speed while maintaining circuit simplicity.
Solution Approach 2:
Multiple ramp signals are pre-generated to cover different sub-ranges of the input voltage. These ramp signals are prepared in advance, allowing the system to immediately compare the input signal against the appropriate ramp without waiting for a single ramp to reach the required level, thus speeding up the conversion process.
2Productivity
If a successive approximation ADC is used, then the operation speed is faster, but separate DACs are needed for each channel increasing system complexity
Solution Approach 1:
Multiple ramp signals that would traditionally require separate DACs are merged into a single ramp generator circuit. This unified approach generates all ramp signals simultaneously using shared components, achieving fast conversion speeds without the complexity of multiple DACs and their matching requirements.
Solution Approach 2:
A single ramp generator is designed to produce multiple ramp signals that serve different sub-ranges. This multi-functional generator replaces what would otherwise require multiple dedicated DACs, reducing system complexity while maintaining the fast operation characteristics of successive approximation methods.
3Productivity
If multiple non-overlapping ramp signals are used to cover sub-ranges, then the comparison process is accelerated and power consumption is reduced, but the system requires more complex ramp signal generation
Solution Approach 1:
The ramp signal generation function is merged into a single unified circuit that produces multiple ramp signals simultaneously. By combining what would otherwise be separate generation circuits, the patent achieves fast comparison speeds across multiple sub-ranges without proportionally increasing the complexity of the generation system.
Data Source
AI summary
A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.