Multiple Row Buffers for DRAM Bank Groups
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Solution Overview
Problem
Existing DRAM devices are limited in memory access efficiency due to the association of a single row buffer with each bank, which restricts the caching scheme's effectiveness.
Innovation Solution
Implementing multiple row buffers per bank or across a group of banks, allowing for either dedicated or shared usage, to enhance memory access efficiency by managing row buffer assignment either by the host or the memory sub-system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single row buffer is associated with each bank, then the device complexity is reduced, but the memory access efficiency deteriorates
Solution Approach 1:
The patent divides the row buffer resource into multiple independent buffers (first row buffer and second row buffer) associated with each bank, allowing simultaneous caching of multiple rows. This segmentation enables parallel memory access operations, improving memory access efficiency without significantly increasing overall system complexity.
Solution Approach 2:
The patent introduces a new dimension to the row buffer architecture by implementing multiple row buffers per bank instead of a single buffer. This dimensional expansion allows the system to cache multiple rows simultaneously, transforming the memory access pattern from sequential to parallel, thereby improving productivity.
2Reliability
If multiple row buffers are implemented per bank, then the caching effectiveness is improved, but the device complexity increases
Solution Approach 1:
The row buffer resource is segmented into multiple independent buffers (first row buffer and second row buffer), each capable of caching a separate row. This segmentation improves caching effectiveness by allowing simultaneous storage of multiple rows, enhancing the reliability of the caching mechanism.
Solution Approach 2:
The multiple row buffers are designed to be universally applicable across different banks and can be selectively activated based on access patterns. This multi-functionality approach improves caching effectiveness while managing complexity through flexible, context-dependent buffer utilization.
3Adaptability or versatility
If row buffer assignment is managed by the host, then the adaptability is improved, but the ease of operation deteriorates
Solution Approach 1:
The memory device autonomously manages row buffer assignment and selection without requiring explicit host intervention. The device automatically selects which row buffer to use based on the bank and row address, improving ease of operation while maintaining adaptability through intelligent, context-aware buffer management.
Solution Approach 2:
The system incorporates feedback mechanisms where the memory device monitors access patterns and dynamically adjusts row buffer assignment. This feedback-driven approach improves adaptability to different workloads while simplifying operation for the host, as the system self-optimizes based on observed behavior.
Data Source
AI summary
An example memory sub-system includes: a plurality bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each bank group; and a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving, from a host, a command identifying a row buffer of the plurality of row buffers; and perform an operation with respect to the identified row buffer.