Multiple Silicide Integration for CMOS and Bipolar Transistors
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Solution Overview
Problem
In advanced integrated circuits, a single silicide process for forming silicide regions on both CMOS and other types of devices, such as bipolar transistors, leads to step height differences and varying contact widths, causing processing difficulties and non-uniform sheet resistance, which negatively impact device functionality and yield.
Innovation Solution
A method involving separate silicide regions with different materials and thicknesses is applied to each type of transistor, using protective layers to expose and form silicide contacts specifically tailored for CMOS and bipolar devices, allowing for optimized sheet resistance and reduced processing challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single silicide process is used for both CMOS and bipolar devices, then manufacturing simplicity is maintained, but device functionality and yield deteriorate due to step height differences and non-uniform sheet resistance
Solution Approach 1:
The patent divides the silicide formation process into separate sequential processes for CMOS devices and bipolar devices. First, a first silicide is formed on CMOS devices, then a second silicide is formed on bipolar devices. This segmentation allows each device type to receive optimized silicide treatment, resolving the conflict between manufacturing simplicity and device functionality by trading process complexity for improved reliability.
Solution Approach 2:
The patent applies different silicide materials and parameters to different device regions. CMOS devices receive a first silicide with specific properties while bipolar devices receive a second silicide with different properties. This local differentiation ensures that each device type receives the optimal silicide characteristics for its specific requirements, improving overall device functionality and yield.
2Manufacturing precision
If different silicide materials and thicknesses are used for different device types, then sheet resistance optimization is achieved, but process complexity increases
Solution Approach 1:
The silicide formation is segmented into distinct sequential processes, with each process optimized for a specific device type. This allows precise control over silicide material composition and thickness for each device category, achieving the desired sheet resistance optimization while managing process complexity through systematic division of steps.
Solution Approach 2:
The patent changes key silicide parameters (material composition, thickness, formation temperature) between the first and second silicide processes. By adjusting these parameters specifically for each device type, the patent achieves optimized sheet resistance characteristics tailored to the electrical requirements of CMOS versus bipolar devices.
3Ease of manufacture
If a single silicide process is used, then manufacturing cost is reduced, but processing difficulties such as over-etching occur
Solution Approach 1:
By segmenting the silicide formation into separate processes, the patent eliminates processing difficulties that arise from attempting to treat diverse device types simultaneously. Each segmented process can be optimized with appropriate etching and deposition parameters, preventing over-etching and other processing defects while managing cost through efficient process design.
Solution Approach 2:
The patent performs preliminary silicide formation on CMOS devices before forming silicide on bipolar devices. This preliminary action allows optimization of the first process without concern for bipolar device requirements, and the second process can then be independently optimized for bipolar devices, preventing processing difficulties through staged optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables optimized silicide regions for each device type, reducing step height differences and processing difficulties, improving device functionality and yield while minimizing costs.
Implementation Method 1
A first protective layer is formed over the first type of transistor such that the second type of transistor is exposed
Implementation Method 2
a first silicide is formed on the second type of transistor
Implementation Method 3
The first protective layer is removed from the first type of transistor
Implementation Method 4
a second protective layer is formed over the second type of transistor such that the first type of transistor is exposed
Implementation Method 5
A second silicide is formed on the first type of transistor, the second silicide having at least one characteristic that is different than the first silicide
Data Source
AI summary
A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.