Multiple Stride Prefetching for Nested Loop Address Prediction
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Solution Overview
Problem
Existing data processing systems face challenges in accurately predicting memory addresses for prefetching due to complex stride patterns, especially in nested loops, which can lead to inefficient prefetching when the inner loop iteration count is small.
Innovation Solution
The system employs stride determination circuitry to identify multiple stride values and store them in a table data structure, allowing for the identification of multi-stride patterns and prediction of future addresses, with a prefetch initiation mechanism that modifies current addresses using matching stride values to retrieve data values before they are actually requested.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simple single-stride prefetching is used, then the prefetching mechanism is simple and fast, but it cannot accurately predict addresses in nested loops with small inner loop iteration counts
Solution Approach 1:
The patent segments the stride determination into multiple independent components: a first stride determination circuit for inner loop strides and a second stride determination circuit for outer loop strides. Each circuit independently analyzes stride patterns in its respective loop level, allowing accurate prediction of complex multi-stride address patterns without requiring a single overly complex prediction mechanism.
Solution Approach 2:
The patent transitions from single-stride prediction to multi-dimensional stride prediction by introducing multiple stride values (first stride and second stride) that operate at different loop levels. This dimensional expansion allows the system to capture complex address patterns in nested loops by combining strides from different dimensions (inner and outer loop iterations).
2Measurement precision
If multiple stride values are determined and stored, then address prediction accuracy improves, but the storage requirement and circuit complexity increase
Solution Approach 1:
The patent applies local quality by storing stride values in specific locations associated with their corresponding loop levels. The first stride values are stored in association with inner loop iterations, while second stride values are stored in association with outer loop iterations. This localized storage approach allows the system to maintain accurate stride information without requiring a single large unified storage structure, optimizing the balance between storage efficiency and prediction accuracy.
Data Source
AI summary
Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.