Multiple-Stripe RAID Memory for Reads During Flash Writes
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Solution Overview
Problem
Current computer memory systems face bottlenecks due to high latency and variable access times in persistent storage, particularly in large data sets, which are exacerbated by the asymmetry between read and write operations in FLASH memory, leading to performance issues and complexity in managing data access.
Innovation Solution
A memory system with multiple modules is configured to perform write or erase operations in a controlled manner, allowing simultaneous reading without blockage by ensuring only one module performs these operations at a time, and using error-correcting codes to reconstruct data from parity data stored across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are used to store large data sets, then storage capacity increases, but access latency increases due to the need to read from multiple modules
Solution Approach 1:
The patent segments data into multiple stripes distributed across different memory modules, where each stripe contains a portion of the data and associated parity information. This segmentation allows the system to read only the necessary stripes rather than accessing entire modules, reducing access latency while maintaining storage capacity.
Solution Approach 2:
The patent introduces parity data as an intermediary element that enables data reconstruction without requiring access to all original memory modules. By storing parity information in a separate module, the system can recover data from failed or busy modules, reducing access latency and improving reliability.
2Productivity
If write operations are performed on multiple memory modules simultaneously, then write throughput increases, but read operations are blocked due to module unavailability
Solution Approach 1:
The patent divides write operations into sequential phases across different memory modules, ensuring that only one module performs write operations at any given time. This segmentation prevents read blockage while maintaining acceptable write throughput by allowing other modules to service read requests simultaneously.
Solution Approach 2:
The patent implements periodic write operations where memory modules alternate between write and read phases. During write phases, modules perform write operations in a controlled sequence; during read phases, modules are available for read operations. This periodic scheduling reduces read blockage time while maintaining write throughput.
3Reliability
If error-correcting codes are used to reconstruct data from parity, then data reliability improves, but computational complexity increases
Solution Approach 1:
The patent changes the error correction approach by using simple XOR operations instead of complex error-correcting codes. By altering the mathematical parameters of error correction to use bitwise XOR operations, the system achieves data reliability through parity reconstruction while minimizing computational complexity.
Solution Approach 2:
The patent uses simple, computationally inexpensive XOR operations for error correction instead of complex, resource-intensive error-correcting codes. These simple operations act as 'cheap' computational objects that provide sufficient reliability for the application while minimizing computational overhead and complexity.
Data Source
AI summary
A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.