Multiple-Vt FET Gate Stack for Precise Threshold Voltage Tuning
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Solution Overview
Problem
Current methods for manufacturing multi-threshold voltage (Vt) field-effect transistors (FETs) face challenges in scaling down to smaller nodes, as they struggle to provide precise Vt modulation due to random dopant fluctuation and limited space, leading to unacceptably large variations in threshold voltage, which affects device performance and power consumption in CMOS circuits.
Innovation Solution
A field-effect transistor (FET) device with a modulated threshold voltage is achieved by combining an ultrathin dielectric dipole layer and a high-k insulating layer with a doped gate metal layer, allowing for independent and concurrent fine-tuning of Vt values, enabling precise control of Vt shifts within a narrow range suitable for extreme scaled nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional Vt modulation methods are used, then manufacturing process is simpler, but Vt modulation precision deteriorates due to random dopant fluctuation
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate stack by introducing an ultrathin dielectric dipole layer with specific properties (thickness <1nm, high dipole moment) to modulate the threshold voltage. This approach replaces conventional dopant-based Vt control with a parameter-based control mechanism that achieves precise Vt modulation without random fluctuations.
Solution Approach 2:
The patent employs a composite gate stack structure combining multiple materials: ultrathin dielectric dipole layer, high-k insulating layer, and metal gate layer. This composite structure integrates the advantages of each material to achieve both precise Vt modulation and compatibility with scaled device architectures.
2Productivity
If device size is scaled down, then device density increases, but Vt control deteriorates due to limited space and increased dopant fluctuation
Solution Approach 1:
The patent transitions from controlling Vt through three-dimensional dopant distribution to controlling it through the two-dimensional interface properties of the ultrathin dielectric dipole layer. This dimensional shift enables precise Vt control in scaled devices where dopant placement variability becomes unacceptable.
Solution Approach 2:
The patent applies local quality by creating an ultrathin dielectric dipole layer with specific local properties (high dipole moment, controlled thickness) at the gate-channel interface. This localized modification enables precise Vt control without affecting the overall device architecture or requiring dopant insertion in the channel region.
3Manufacturing precision
If dipole layer thickness is reduced, then Vt modulation precision improves, but manufacturing difficulty increases
Solution Approach 1:
The patent replaces conventional thick-layer deposition techniques with advanced atomic-layer deposition (ALD) methods that can precisely control ultrathin layer thickness at the nanometer and sub-nanometer scale. This substitution enables manufacturing of the required ultrathin dipole layer with atomic-level precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise modulation of Vt values, reducing variations and improving power efficiency and computing speed in CMOS circuits, while meeting stringent future RMG spacing specifications, even at nodes smaller than 10 nm.
Implementation Method 1
an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction
Implementation Method 2
a high-k (HK) insulating layer on the ultrathin dielectric dipole layer
Implementation Method 3
a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction
Data Source
AI summary
A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.