Multiple-Well MOSFET Layout for Gate Bounce and Switching Loss
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Solution Overview
Problem
Metal oxide semiconductor field effect transistors (MOSFETs) face challenges with gate bounce induced shoot-through and switching loss due to capacitance variations between the gate electrode and lightly doped drain (LDD) regions, which can lead to voltage breakdown and increased power dissipation.
Innovation Solution
A MOSFET design with a variable thickness gate dielectric layer and asymmetric dopant concentration profiles under the spacer layers adjacent to the source and drain regions, optimizing the first capacitance (Cgs) to reduce gate bounce while minimizing the second capacitance (Cgd) to reduce switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dopant concentration of the LDD regions is increased to increase capacitance, then the conductivity of the LDD regions increases resulting in increased capacitance, but this leads to gate bounce induced shoot-through and voltage breakdown
Solution Approach 1:
The patent applies local quality by creating different dopant concentration profiles in different regions: the first LDD region has a higher dopant concentration than the second LDD region. This asymmetric doping strategy locally optimizes capacitance in the source region (first LDD) while maintaining lower capacitance in the drain region (second LDD) to prevent gate bounce induced shoot-through, thus resolving the contradiction between achieving sufficient capacitance and preventing voltage breakdown.
2Quantity of substance
If the dopant concentration of the LDD regions is increased to increase capacitance, then the conductivity of the LDD regions increases resulting in increased capacitance, but this leads to increased power dissipation
Solution Approach 1:
The patent implements local quality by differentiating dopant concentrations between the first and second LDD regions. The first LDD region (source side) has higher dopant concentration to provide necessary capacitance for switching performance, while the second LDD region (drain side) has lower dopant concentration to minimize capacitance and reduce power dissipation during switching operations, thereby resolving the contradiction between capacitance requirements and energy loss.
3Ease of manufacture
If a symmetric dopant concentration profile is used in LDD regions, then manufacturing is simplified, but capacitance optimization for reducing both gate bounce and switching loss cannot be achieved
Solution Approach 1:
The patent directly applies asymmetry by specifying that the first LDD region has a higher dopant concentration than the second LDD region. This asymmetric doping profile is intentionally designed to create different capacitance values (Cgs and Cgd) that can independently optimize both gate bounce reduction and switching loss minimization, resolving the contradiction between manufacturing simplicity and capacitance optimization performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the risk of gate bounce induced shoot-through and minimizes switching loss, enhancing the performance and reliability of MOSFETs by balancing capacitance to prevent voltage breakdown and power dissipation issues.
Implementation Method 1
A first capacitor Cgs is formed between the gate electrode and the LDD region on the source side of the MOSFET, and a second capacitor Cgd is formed between the gate electrode and the LDD region on the drain side of the MOSFET
Implementation Method 2
An amount of capacitance in the first capacitor Cgs and the second capacitor Cgd is determined by a dopant concentration in the LDD regions and by an amount of overlap of the LDD regions with the gate electrode
Data Source
AI summary
A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.