Multiplexing Data Flows via Shared Transfer Ring

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Solution Overview

Problem

Existing inter-processor communication technologies, such as PCIe, face challenges in mobile devices due to high memory consumption and power constraints, as they pre-allocate memory for data pipes even when not actively used, leading to inefficiencies in memory management and performance.

Innovation Solution

The implementation of a method and apparatus that utilize a common data structure, like a transfer ring, to multiplex and de-multiplex data flows between multiple processors, allowing for efficient memory management by allocating a fixed memory space and freeing completed portions, thereby optimizing memory usage and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-allocation of memory for data pipes is used, then data transfer capability is improved, but memory consumption increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidmemory consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the memory management approach by introducing individual completion pipes for tracking data transfer status, while using a shared transfer ring for actual data transmission. This allows the system to maintain reliable data transfer capability through dedicated completion tracking while reducing overall memory consumption by sharing the transfer ring among multiple data pipes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple data pipe transfer operations into a single shared transfer ring structure. Instead of each data pipe having dedicated memory space, multiple data pipes share the same transfer ring, reducing memory consumption while maintaining the ability to handle multiple concurrent data transfers through the completion pipe mechanism.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If pre-allocation of memory for data pipes is used, then data transfer capability is improved, but power consumption increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces dynamic memory management where memory is allocated and freed based on actual data transfer needs rather than being pre-allocated for all possible data pipes. The completion pipe mechanism allows the system to dynamically track and manage memory usage, freeing resources when data transfers are complete, thereby reducing power consumption while maintaining data transfer capability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements memory recovery by freeing completed portions of the transfer ring back into the pool of available memory. This allows the system to discard unused memory allocations and recover resources, reducing overall power consumption by ensuring memory is only allocated for active data transfers rather than being continuously held in pre-allocated state.

Inventive Principle:
Principle #34Discarding and recovering

3Loss of information

If individual completion pipes are used for each data pipe, then data flow tracking is improved, but device complexity increases

Engineering Contradiction:
Improvedata flow tracking accuracyVSAvoidstructure complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent makes the completion pipe mechanism universal by using a single shared structure that serves all data pipes. Instead of having separate completion pipe implementations for each data pipe, the system uses a unified completion tracking mechanism that works across multiple data pipes, reducing structural complexity while maintaining accurate data flow tracking through the shared ring buffer approach.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11347567B2Methods and apparatus for multiplexing data flows via a single data structure
Publication Date: 2022.05.31 APPLE INC
  • US11347567B2 patent drawing
  • US11347567B2 patent drawing
  • US11347567B2 patent drawing

AI summary

Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.