Multiplexed Command/Address Bus for NVDIMM Signal Integrity
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Solution Overview
Problem
NVDIMMs face challenges in maintaining predictable electrical impedance on the command/address bus due to the inclusion of a command/address multiplexer, especially as memory capacity increases, which complicates compatibility with both host devices and onboard controllers.
Innovation Solution
Implementing a multiplexed command/address bus system that routes command/address signals through both a registering clock driver and a controller, allowing for independent signal level adjustment to match the design specifications of volatile memories, thereby ensuring predictable electrical load and improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a command/address multiplexer is added to support both host device and controller connections, then adaptability is improved, but device complexity increases
Solution Approach 1:
The command/address bus is designed to serve multiple functions by connecting to both the host device interface and the controller through a multiplexer, allowing the same physical bus to be universally used for different operational modes (normal host access and controller management)
Solution Approach 2:
A command/address multiplexer is introduced as an intermediary component that mediates between the host device interface, the controller, and the volatile memory, intelligently routing commands and addresses to the appropriate destination based on the current operational mode
2Productivity
If memory capacity is increased to provide higher density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple memory technologies (volatile DRAM and non-volatile memory) into a single NVDIMM module, achieving higher effective memory capacity while consolidating the overall system architecture rather than requiring separate memory systems
3Reliability
If electrical impedance requirements are made more stringent to meet standard format demands, then reliability is improved, but ease of manufacture worsens
Solution Approach 1:
The patent applies different electrical characteristic optimizations to different parts of the system - the host interface maintains standard DIMM electrical characteristics while the controller interface and internal routing are optimized for their specific requirements, allowing each section to meet its particular reliability standards
Data Source
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AI summary
A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.