Multiplexed Bus Streak Management in MRDIMM Pseudo Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current MRDIMM systems face challenges in designing modular circuitry for pseudo channels due to the need for simultaneous read or write operations to avoid bus contention, making it difficult to optimize memory access speed and scalability.
Innovation Solution
The implementation of a cross mode condition in the arbitration circuitry allows pseudo channels to independently switch between read and write modes, ensuring that both channels operate in the same mode at the same time, thereby avoiding bus contention and enabling modular circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pseudo channels operate independently with separate arbitration circuitry, then memory access speed and scalability are improved, but bus contention occurs when channels need to operate simultaneously
Solution Approach 1:
The patent segments the arbitration process into two independent stages: a first arbitration stage that independently selects commands for each pseudo channel, and a second arbitration stage that coordinates between channels to ensure they operate in the same mode simultaneously. This segmentation allows each channel to be optimized for speed while maintaining coordination to avoid bus contention.
Solution Approach 2:
The patent introduces a cross-mode condition as an intermediary mechanism that mediates between the independent operation of pseudo channels and the requirement for simultaneous mode operation. The cross-mode condition acts as a coordinator that allows channels to operate independently most of the time while providing a controlled interaction point when mode switching is needed, thus avoiding bus contention.
2Ease of manufacture
If modular circuitry is designed for each pseudo channel, then ease of manufacture and scalability are improved, but the need for simultaneous mode operation complicates the design
Solution Approach 1:
The patent designs the arbitration circuitry with universality by creating a shared cross-mode condition mechanism that serves both pseudo channels. Instead of requiring completely separate arbitration circuits for each channel, the system uses a common coordination mechanism that both channels can independently utilize, reducing overall device complexity while maintaining modular design benefits.
Solution Approach 2:
The arbitration circuit is segmented into independent first arbitration stages for each pseudo channel, allowing each channel to have its own simplified arbitration logic. The complexity is then distributed to a shared second arbitration stage that handles coordination between channels, making the overall design more manageable and scalable.
3Ease of manufacture
If pseudo channels use the same bus interface, then chip cost is reduced, but simultaneous read and write operations cause bus contention
Solution Approach 1:
The patent ensures continuous useful action by maintaining independent command selection for both pseudo channels while using the cross-mode condition to coordinate mode switching. This allows the system to maintain high memory access efficiency by avoiding idle periods where channels would need to wait for bus availability, while still using a single shared bus interface to reduce chip cost.
Data Source
AI summary
A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.