Multiplexed Clock Distribution for Backplane Wiring Reduction

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Solution Overview

Problem

The layout of clock lines for clock distribution in communication equipment is complicated and ineffective due to the exponential increase in the number of lines required for multiple frequency sources, which is exacerbated by the limited space in the backplane for wiring.

Innovation Solution

An apparatus and method for sending and receiving clocks that utilize an input unit to input multiple clocks, a sampling unit to determine frequency control words indicative of the relationship between sampling clocks, and a sending unit to generate a clock signal carrying these frequency control words, allowing for the transmission of clocks from different frequency sources over the same clock line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple clock lines are arranged for different frequency sources, then clock distribution capability is improved, but the number of lines increases exponentially and wiring complexity increases

Engineering Contradiction:
Improveclock distribution capabilityVSAvoidwiring complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple clock signals from different frequency sources into a single clock line by multiplexing. The sending apparatus combines first and second clock signals from different frequency sources onto one transmission line, and the receiving apparatus separates them using a demultiplexer. This reduces the number of clock lines from potentially dozens to just one or a few, dramatically simplifying the wiring complexity while maintaining the ability to distribute multiple clock frequencies throughout the communication equipment.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes a single clock line universal by enabling it to carry multiple clock signals from different frequency sources. Instead of dedicating separate lines to each frequency source, one clock line can serve multiple functions by transmitting different clock signals at different times or in a multiplexed manner. This multi-functionality approach allows the same physical infrastructure to support diverse clock distribution needs without requiring proportional increases in wiring.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple clock lines are arranged for different frequency sources, then clock distribution capability is improved, but the space required in the backplane increases

Engineering Contradiction:
Improveclock distribution capabilityVSAvoidbackplane space
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple clock signals from different frequency sources into a single clock line by multiplexing. The sending apparatus combines first and second clock signals from different frequency sources onto one transmission line, and the receiving apparatus separates them using a demultiplexer. This reduces the number of clock lines from potentially dozens to just one or a few, dramatically simplifying the wiring complexity while maintaining the ability to distribute multiple clock frequencies throughout the communication equipment.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a spatial multiplexing approach (multiple parallel lines) to a temporal multiplexing approach (single line used at different times). Instead of allocating separate physical paths for each clock signal in the spatial dimension, the system uses the time dimension to separate different clock signals on the same physical line. This dimensional shift dramatically reduces the area required in the backplane while preserving full clock distribution capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If the number of clock lines is reduced, then wiring complexity and space usage are improved, but clock signal transmission accuracy may deteriorate

Engineering Contradiction:
Improvewiring complexityVSAvoidclock signal transmission accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary multiplexing mechanism that carefully manages the combination and separation of clock signals. The multiplexer at the sending end and demultiplexer at the receiving end act as intelligent intermediaries that preserve the integrity of each clock signal while sharing the transmission medium. This intermediary approach ensures that despite the reduced number of physical lines, each clock signal maintains its transmission accuracy through proper timing, synchronization, and signal separation protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12273112B2Clock sending apparatus and method, and clock receiving apparatus and method
Publication Date: 2025.04.08 ZTE CORP
  • US12273112B2 patent drawing
  • US12273112B2 patent drawing
  • US12273112B2 patent drawing

AI summary

A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.