Multiplexed Command Bus for NVDIMM Signal Integrity
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Solution Overview
Problem
NVDIMMs face challenges in maintaining predictable electrical impedance on command/address buses due to increased memory capacity, complicating compatibility with both host devices and onboard controllers, especially when additional circuitry is required for non-volatile memory management.
Innovation Solution
Implementing a multiplexed command/address bus architecture within memory devices, which includes a registering clock driver and a controller connected through data multiplexers to manage signal integrity and impedance, allowing for higher memory densities and improved signal integrity by routing command/address signals effectively between the host, RCD, and non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional circuitry is added to NVDIMM for non-volatile memory management, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent combines the command/address bus used by the host with the command/address bus used by the non-volatile memory controller into a single shared bus. This merging eliminates the need for separate dedicated buses, reducing circuitry complexity while maintaining full functionality for both volatile and non-volatile memory operations.
Solution Approach 2:
The command/address bus is designed to serve multiple functions: it carries commands from the host to volatile memory, commands from the non-volatile memory controller to volatile memory, and supports various memory operations. This multi-functionality reduces the need for dedicated circuitry for each function, thereby reducing overall device complexity.
2Productivity
If memory capacity is increased in NVDIMM, then productivity is improved, but electrical impedance predictability deteriorates
Solution Approach 1:
By merging the host command/address bus and controller command/address bus into a single shared bus, the patent reduces the total number of signal paths. This reduction in bus complexity helps maintain predictable electrical impedance characteristics even as memory capacity increases, because there are fewer interconnected circuits to create impedance variations.
3Device complexity
If multiplexed command/address bus is implemented, then device complexity is reduced, but signal integrity may deteriorate
Solution Approach 1:
The patent incorporates a registering clock driver that performs preliminary signal registration and conditioning before signals are routed through the multiplexed bus. This preliminary action ensures that signals are properly conditioned and timed, maintaining signal integrity despite the bus being shared between multiple sources and destinations.
Solution Approach 2:
The registering clock driver acts as an intermediary between the bus sources (host and non-volatile memory controller) and the bus destinations (volatile memory). It mediates signal timing and conditioning, ensuring that multiplexed signals maintain their integrity when shared across the common bus.
Data Source
AI summary
A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.