Hierarchical Multiplexed Counters for High-Speed Overflow Scaling
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Solution Overview
Problem
High-speed network devices face challenges in efficiently storing and updating statistics counters due to the tradeoff between using expensive on-chip SRAM and the limitations of off-chip DRAM, where there is a need to balance the number of counters to avoid integer overflow while efficiently utilizing memory resources.
Innovation Solution
The implementation of hierarchical statistically multiplexed counters, which dynamically concatenate P base counters with S subcounters across multiple levels, using an overflow FIFO to extend counter life and manage overflows, allowing flexible expansion and shrinkage of counter capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If off-chip DRAM is used to store counters, then memory cost is reduced, but counter update speed cannot meet high speed requirements
Solution Approach 1:
The counter storage is segmented into multiple levels: on-chip SRAM stores base counters and subcounters for high-speed updates, while off-chip DRAM stores overflow information through FIFO queues. This segmentation allows the system to utilize the high speed of SRAM for frequent operations while using the low cost of DRAM for less frequent overflow data, resolving the contradiction between cost and speed.
Solution Approach 2:
Overflow FIFO queues act as intermediaries between on-chip SRAM and off-chip DRAM. When counters overflow, the overflow information is temporarily stored in the FIFO queue before being transferred to DRAM. This intermediary mechanism decouples the high-speed update requirement from the low-cost storage requirement, allowing SRAM to maintain high speed while DRAM provides cost-effective bulk storage.
2Duration of action of moving object
If the number of counters is increased to avoid integer overflow, then counter life is extended, but memory resource utilization becomes inefficient
Solution Approach 1:
The counter architecture dynamically adjusts its capacity by combining base counters and subcounters. When the counter value approaches overflow, subcounters are dynamically concatenated to extend the counting range. This dynamic adjustment allows the system to extend counter life only when necessary, rather than permanently allocating maximum memory resources, thus resolving the contradiction between counter life extension and memory efficiency.
Solution Approach 2:
Subcounters are nested within the counter structure and can be dynamically concatenated with base counters to extend counting capacity. This nested structure allows the system to effectively increase counter life by utilizing additional counting bits from subcounters only when the base counters are nearing overflow, thereby extending counter life without permanently allocating the maximum possible memory resources.
3Speed
If on-chip SRAM is used to store counters, then counter update speed is improved, but memory cost increases significantly
Solution Approach 1:
The system applies local quality by using on-chip SRAM only for the portion of counter storage that requires high-speed updates (base counters and active subcounters), while using off-chip DRAM for overflow information storage. This localized use of expensive high-speed memory only where necessary resolves the contradiction between speed improvement and cost increase.
Solution Approach 2:
Counter storage is segmented into high-speed SRAM-resident base counters and subcounters, and low-cost DRAM-resident overflow FIFO queues. This segmentation allows the system to achieve high counter update speeds for normal operations using SRAM, while utilizing inexpensive DRAM for storing overflow information that occurs less frequently, thereby resolving the cost-speed contradiction.
4Ease of manufacture
If fixed-size counters are used, then implementation is simpler, but counter life is limited due to integer overflow
Solution Approach 1:
The counter system transitions from fixed-size to dynamic-size counters by enabling the concatenation of subcounters with base counters when overflow is detected. This dynamic adjustment maintains implementation simplicity through standardized counter structures while extending counter life by adaptively increasing counting capacity only when needed, resolving the contradiction between simplicity and counter life.
Data Source
AI summary
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.