Multiplexed Digit Lines With Two-Transistor Cell Isolation
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Solution Overview
Problem
As memory cell densities increase, undesired disturbances occur due to voltage changes being capacitively coupled between neighboring digit lines, affecting the logic states of memory cells, which can be mitigated by incorporating a selection component with two transistors to isolate memory cells during read operations.
Innovation Solution
A memory cell design with a selection component comprising two transistors, where one transistor is activated by a word line and the other by a select line, isolates memory cells from neighboring digit lines, reducing disturbances and allowing multiplexing of digit lines with a sense component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If word lines are activated to read data from multiple memory locations, then data can be retrieved from multiple locations simultaneously, but column select signals must be maintained for the entire row decode period causing power consumption
Solution Approach 1:
Column select signals are generated in advance before the row decode period begins, allowing these signals to be turned off after latching rather than being maintained throughout the entire row decode period. This preliminary generation of control signals reduces the duration they must be maintained, thereby reducing power consumption while still enabling simultaneous data retrieval from multiple memory locations.
2Speed
If digit lines are used to read data from multiple memory locations, then read speed improves, but signal integrity degrades due to increased capacitance and interference
Solution Approach 1:
The memory array is divided into multiple banks, each with its own dedicated digit lines. This segmentation allows read operations to be distributed across different physical line sets, reducing the total capacitance and interference on any single digit line while maintaining high read speeds through parallel access to multiple banks.
Solution Approach 2:
Sense amplifiers are introduced as intermediary components between the digit lines and the read data. These sense amplifiers buffer and regenerate the read signals, isolating the digit lines from direct connection to multiple memory cell outputs. This intermediary structure reduces signal interference and capacitance effects on the digit lines while preserving fast read performance.
Data Source
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AI summary
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.