Time-Division Multiplexed Digital Filter for Multi-Channel Decimation
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Solution Overview
Problem
The existing digital filters for processing multiple input channels require a significant circuit scale and cost due to the need for multiple AD converters and digital filters, leading to increased chip area and unit price, especially when implemented on a single silicon chip.
Innovation Solution
A digital filter configuration that includes cascade-connected integration and difference calculation units operating with time-division-multiplexed data, a frequency conversion unit, and a multiplexer to process multiple channels without the need for separate digital filters, reducing circuit scale and cost by sharing resources and using a reduced number of delay units and flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple AD converters and digital filters are provided for multiple input channels, then the processing capability for multiple channels is improved, but the circuit scale and chip area increase significantly
Solution Approach 1:
The patent merges multiple digital filter processing functions into a single shared filter unit. The time-division multiplexing mechanism allows one digital filter to sequentially process multiple input channels, eliminating the need for separate filters for each channel. This combining approach significantly reduces chip area while maintaining multi-channel processing capability.
Solution Approach 2:
The digital filter unit is designed with universal functionality to handle multiple input channels through time-division multiplexing. A single filter unit can process data from different channels at different time slots, making it a multi-functional component that replaces what would traditionally require multiple dedicated filter units.
2Measurement precision
If the bit width of registers is increased to achieve high bit resolution and precision, then the measurement precision is improved, but the circuit scale of addition and subtraction circuits increases
Solution Approach 1:
The patent employs periodic action through time-division multiplexing, where the single digital filter unit alternates between processing different input channels in sequential time slots. This periodic operation allows high-precision processing to be achieved with a single set of high-bit-width circuits rather than multiple parallel circuits, reducing overall device complexity.
Data Source
AI summary
A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency fD×M, decimates data at the sampling frequency fs input from the integration calculation unit (10) in the last stage at a sampling frequency fD, and delays data obtained as a result of decimation by (M−1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency fD×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samples before.