Multi-Die IC Package With Multiplexed Interface
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Solution Overview
Problem
The transition to smaller nanometer technologies in silicon processing leads to a dichotomy between low voltage, high speed digital logic and higher voltage interconnect technologies, causing design challenges such as pad limitations and resource-intensive porting of high speed analog interfaces, especially when implementing complex systems like DDR3 SDRAM and HDMI/SATA/USB3 interfaces within integrated circuits.
Innovation Solution
A package comprising multiple dies, where analog and digital circuitry are decoupled, allowing for different voltage and transistor gate oxide thicknesses on each die, and using a shared interface for control signals and memory transactions to reduce pin count and power consumption, enabling modular design and compatibility with various interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size is decreased to shrink digital logic, then digital logic area is reduced, but pad limitations and resource-intensive porting of high speed analog interfaces occur
Solution Approach 1:
The patent divides the integrated circuit into multiple separate dies - a first die for digital logic and a second die for analog interfaces. This segmentation allows each die to be optimized independently for its specific function, enabling digital logic to shrink to smaller feature sizes while analog interfaces maintain their required voltage levels and physical dimensions, thereby resolving the pad limitations and interface porting complexity issues.
Solution Approach 2:
The patent introduces an interface die or interconnect structure that mediates between the digital logic die and analog interface die. This intermediary component handles the voltage level translation and signal conditioning required for high-speed analog interfaces like DDR3 SDRAM and HDMI, eliminating the need to port these complex interfaces directly onto the shrinking digital logic die.
2Adaptability or versatility
If separate dies are used for analog and digital circuitry, then design flexibility and voltage compatibility are improved, but device complexity and interconnect requirements increase
Solution Approach 1:
The patent merges the digital logic die, analog interface die, and interconnect structure into a single integrated package. This consolidation provides the benefits of separate dies for voltage compatibility and design flexibility while minimizing the external interconnect requirements through optimized packaging and integrated bonding structures.
Solution Approach 2:
The patent employs an intermediary interface die or bonding structure that simplifies the interconnect requirements between separate analog and digital dies. This intermediary component provides standardized connection interfaces and voltage level translation, reducing the overall device complexity despite the multi-die architecture.
3Reliability
If multiple separate interfaces are used for control signals and memory transactions, then signal integrity is improved, but pin count and power consumption increase
Solution Approach 1:
The patent implements a universal interface between the digital logic die and analog interface die that can handle both control signals and memory transactions through the same physical connections. This multi-functional interface reduces the pin count by eliminating the need for separate dedicated interfaces while maintaining signal integrity through proper protocol design and timing control.
Data Source
AI summary
A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are shared by the control signals and the memory transactions.