Multiplexed Memory Interface Buffering Host to DRAM
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Solution Overview
Problem
Current DRAM memory devices face challenges in achieving higher capacity, speed, and reduced cost while efficiently interfacing with processors, particularly due to limitations in bandwidth and pin count requirements.
Innovation Solution
The implementation of a memory device configuration that includes a buffer and a multiplexer circuit between the memory devices and the processor, allowing for wider bandwidth and slower memory devices to be used efficiently, with the multiplexer circuit multiplexing data and command/address pins to reduce pin count and enhance data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices use more pins to increase bandwidth, then data throughput is improved, but pin count requirements and device complexity increase
Solution Approach 1:
The patent combines multiple data pins into a single pin by implementing serial communication protocols. Multiple memory channels are multiplexed through time-division multiplexing, where data from different channels is sequentially transmitted through shared pins. This merging approach maintains high data throughput while significantly reducing the physical pin count required on the memory device.
Solution Approach 2:
The patent makes pins multi-functional by allowing them to serve different purposes at different times. The same pins are used for multiple memory channels, for both address and data transmission, and for bidirectional communication. This universality enables the memory device to achieve high bandwidth with fewer pins by dynamically allocating pin functions based on communication needs.
2Speed
If memory devices operate at higher speeds, then performance is improved, but energy consumption and manufacturing costs increase
Solution Approach 1:
The patent implements dynamic speed adjustment capabilities where the memory device can operate at different clock frequencies based on system requirements. The controller can negotiate and adjust the operating speed dynamically, allowing the system to use higher speeds only when necessary for performance-critical operations, while using lower speeds for routine operations to reduce power consumption and heat generation.
Solution Approach 2:
The patent uses periodic clock cycling and burst transfer modes where data is transmitted in optimized bursts rather than continuous streams. This periodic action allows the memory device to enter low-power states between bursts, reducing average power consumption while maintaining high peak transfer rates when data movement is required.
3Productivity
If memory devices use wider bandwidth interfaces, then data throughput is improved, but pin count and device complexity increase
Solution Approach 1:
The patent transitions from spatial parallelism (multiple pins transmitting simultaneously) to temporal parallelism (multiple channels transmitting sequentially through shared pins). By adding the time dimension to the interface architecture, the system achieves wide bandwidth equivalent to parallel interfaces while using a single physical pin, effectively moving the problem from spatial to temporal domain.
Solution Approach 2:
The patent introduces a controller as an intermediary between the host and memory devices that manages the multiplexing operations. This controller handles the complexity of coordinating multiple channels through shared pins, performing channel selection, data routing, and timing synchronization, thereby isolating the complexity from the memory device itself and simplifying its interface requirements.
Data Source
AI summary
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.