Multi-port Register File with Multiplexed Write Lines
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Solution Overview
Problem
Multi-port register files face challenges in reducing the number of lines while maintaining multiple ports, leading to increased area requirements and routing issues, as the number of ports increases, making it difficult to manage resources effectively.
Innovation Solution
A multi-port register design that uses a single write word line per row and a single write bit line or bit line pair per column, allowing for multiple ports without the need for different write bit lines or word lines, utilizing a write word line generator and multiplexers to enable the selected word line and bit lines for each port operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple write bit lines and write word lines are used for each port, then multiple ports can operate independently, but the number of lines increases leading to larger area and routing complexity
Solution Approach 1:
The patent merges the write bit lines and write word lines across multiple ports by using a single shared write bit line and a single shared write word line for the entire memory array. Multiplexers are used to dynamically connect the appropriate port's data to the shared write bit line and the appropriate row to the shared write word line, allowing multiple ports to share the same physical lines through time-multiplexed access.
Solution Approach 2:
The shared write bit line and write word line serve multiple functions by being dynamically assigned to different ports and different rows through the multiplexer control logic. A single write bit line pair can service data from any of the multiple write ports, and a single write word line can select any row for writing, making the lines universal rather than dedicated to specific ports.
2Adaptability or versatility
If multiple write bit lines and write word lines are used for each port, then multiple ports can operate independently, but routing complexity increases significantly
Solution Approach 1:
The patent combines multiple port-specific write bit lines into a single shared write bit line pair, and multiple port-specific write word lines into a single shared write word line. This merging dramatically reduces the number of routing paths required in the memory array, simplifying the overall routing complexity while maintaining multi-port functionality through multiplexer-based dynamic connection.
3Area of stationary object
If a single write word line and write bit line are used, then area is reduced, but multiple ports cannot independently access different rows simultaneously
Solution Approach 1:
The patent implements periodic time-multiplexed action where the single shared write bit line and write word line are rapidly switched between different ports and rows according to a periodic schedule controlled by the multiplexer control logic. This allows the system to service multiple ports sequentially in a periodic manner, achieving the functional equivalent of simultaneous access while using shared lines, thus maintaining productivity without requiring independent lines for each port.
Solution Approach 2:
The patent introduces dynamic switching through multiplexers that can rapidly reconfigure the connections between ports and the shared write bit lines/word lines. This dynamic reconfiguration allows the system to adaptively allocate the shared lines to different ports and rows based on current access requirements, enabling flexible simultaneous service of multiple ports despite the physical limitation of having only one shared line pair.
Data Source
AI summary
A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal.