Time-Multiplexed Neurosynaptic Core for Area Efficiency
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Solution Overview
Problem
The high cost and inefficiency of manufacturing neurosynaptic chips due to the need for a large number of neurosynaptic cores performing the same functions, leading to repeated layouts and connectivity across chips, which increases resource usage and costs.
Innovation Solution
Implementing a multiplexed neural core circuit with T sets of electronic neurons and axons, interconnected via a synaptic network, allowing for efficient sharing of resources and reducing the number of physical cores required by time-division multiplexing, where each set of axons corresponds to one set of neurons and interconnects through a synaptic interconnection network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple neurosynaptic cores are manufactured to perform the same function, then the computational capability and reliability are improved, but the manufacturing cost and resource usage increase
Solution Approach 1:
The patent merges multiple neurosynaptic cores into a single chip by time-multiplexing their operations. Instead of manufacturing separate chips for each core function, the system uses a single chip with shared resources (memory, interconnects) that are dynamically allocated to T different neural cores through time-division multiplexing, thereby reducing manufacturing cost while maintaining computational capability.
Solution Approach 2:
The neurosynaptic core is designed as a universal, reconfigurable unit that can perform multiple functions by changing its configuration over time. The same physical core can be programmed to implement different neural network layers or functions at different time slots, making it multi-functional and eliminating the need for dedicated hardware for each function.
2Productivity
If neurosynaptic cores are tiled across chips multiple times, then the computational throughput is improved, but the area efficiency and resource allocation worsen
Solution Approach 1:
The patent transitions from a spatial tiling approach (multiple copies of cores distributed across chip area) to a temporal dimension approach (time-multiplexed operation of fewer cores). By allocating time slots rather than physical space, the system achieves high computational throughput without proportionally increasing chip area, thus improving area efficiency.
3Adaptability or versatility
If a large number of neurosynaptic cores are implemented, then the functional versatility is improved, but the power consumption and energy efficiency worsen
Solution Approach 1:
The system implements periodic time-division multiplexing where neural cores are activated in sequential time slots. Instead of all cores operating simultaneously, only the subset of cores needed for the current computational task is activated during each time slot, reducing overall power consumption while maintaining the ability to perform diverse functions through periodic reconfiguration.
Data Source
AI summary
A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.