Multiplexed Oscillator Clock Switching for Frequency Drift Detection
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Solution Overview
Problem
Existing integrated circuit devices with multiplexed oscillators face challenges in detecting excessive fluctuations in oscillation frequency over long-term operation, which is not adequately addressed by current technologies using two oscillators, as they cannot handle frequency rises or drops effectively.
Innovation Solution
An integrated circuit device with two oscillators that compares and monitors the frequencies of the clock signals, selecting the output clock signal based on frequency tolerance ranges and switching between them to maintain operational stability, even when one oscillator's frequency deviates, thereby handling excessive fluctuations with a reduced number of oscillators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three or more oscillators are used for multiplexed operation with average value comparison, then functional safety and abnormality detection capability are improved, but device complexity and circuit scale increase
Solution Approach 1:
The patent extracts the essential function of frequency comparison from a multi-oscillator system and implements it using a single oscillator with frequency division. By taking out the comparison function and implementing it separately through frequency division by 2 and 3, the system achieves abnormality detection without requiring multiple oscillators, thus reducing circuit scale while maintaining functional safety
Solution Approach 2:
The patent creates virtual copies of oscillator outputs through frequency division. Instead of using multiple physical oscillators, it generates multiple frequency-divided signals (divided by 2 and 3) from a single oscillator, which then serve as proxies for comparison. This copying approach allows the system to detect abnormalities without the complexity of multiple oscillators
2Duration of action of stationary object
If two oscillators are used for operation clock and standby clock, then operational continuity is improved, but capability to detect frequency fluctuations is insufficient
Solution Approach 1:
The patent introduces frequency-divided signals as intermediaries between the oscillator output and the switching decision. By dividing the oscillator frequency by 2 and 3, and comparing these divided signals with the original clock signal, the system gains the ability to detect frequency fluctuations that would otherwise be undetectable with a simple two-oscillator standby system
Solution Approach 2:
The patent implements feedback by continuously comparing the phase relationship between the original clock signal and the frequency-divided signals. The switching control unit monitors these comparisons and switches oscillators based on detected abnormalities, creating a closed-loop system that maintains frequency accuracy and detects fluctuations that a simple standby system would miss
3Device complexity
If a single oscillator is used without frequency comparison, then device complexity is reduced, but functional safety and reliability decrease
Solution Approach 1:
The patent segments the frequency verification function into multiple frequency division operations (division by 2 and 3). By dividing the oscillator frequency into multiple segments and comparing each segment with the original clock signal, the system achieves comprehensive frequency verification and abnormality detection using only a single oscillator, thus maintaining reliability while reducing device complexity
Solution Approach 2:
The patent introduces dynamic switching capability that allows the system to change oscillators based on detected abnormalities. The switching control unit dynamically selects between first and second oscillators based on real-time frequency comparison results, enabling the single-oscillator system to adapt to failures and maintain functional safety through dynamic reconfiguration
Data Source
AI summary
An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal.