Multiplexed Sample-and-Hold Circuit for Long-Interval Leakage Reduction
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Solution Overview
Problem
Sample and hold circuits face significant leakage errors due to charge changes on hold capacitors, especially in applications requiring high precision over long periods, which current technologies fail to adequately minimize.
Innovation Solution
A signal processing circuit design incorporating a first and second sample and hold circuit with a hold capacitor, input and output switches, and a signal path amplifier, where a voltage feedback amplifier is used to increase the effective resistance of the input switch by a factor of at least 100, reducing leakage through the use of series switches and a clock circuit for controlled switch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional sample and hold circuit is used, then the circuit structure is simple, but leakage through the input switch causes significant error during long hold intervals
Solution Approach 1:
The patent implements a feedback mechanism where the output of the signal path amplifier is fed back to the internal node of the input switch through a feedback switch. This feedback loop compensates for charge leakage by actively maintaining the voltage at the internal node, thereby reducing leakage errors during the hold interval without requiring a completely redesigned circuit architecture
Solution Approach 2:
The patent introduces an internal node as an intermediary between the input switch and the hold capacitor. This internal node serves as a buffer point that allows the feedback mechanism to act on the switch output without directly loading the hold capacitor, thus isolating the capacitor from leakage effects while maintaining circuit simplicity
2Duration of action of stationary object
If the hold interval is extended for long period signal retention, then signal holding duration is improved, but leakage errors increase significantly
Solution Approach 1:
The feedback mechanism operates continuously during the hold interval, constantly compensating for leakage currents. The feedback switch remains closed throughout the hold period, maintaining continuous active correction of charge loss, which enables long-duration holding without degradation in accuracy
Solution Approach 2:
The continuous feedback loop actively monitors and corrects leakage effects in real-time during extended hold intervals, allowing the circuit to maintain high accuracy even over long periods by dynamically compensating for charge loss through the feedback path
3Device complexity
If multiple sample and hold circuits share a common output node, then circuit integration is improved, but crosstalk between channels increases
Solution Approach 1:
The internal node acts as an intermediary that isolates the hold capacitor from direct interaction with other circuit channels. By placing the feedback connection at this intermediate point rather than directly at the output, the circuit reduces coupling between multiple channels sharing the common output node, thereby minimizing crosstalk while maintaining integration
Data Source
AI summary
A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.