Multiplexed Serial Media Independent Interface Pin Reduction

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Solution Overview

Problem

Network devices face significant production cost and layout challenges due to the high number of conductors (pins) required for interfacing between Media Access Control (MAC) and Physical Layer (PHY) circuits, especially in high-speed Ethernet applications.

Innovation Solution

A multiplexed serial media independent interface system that communicates data between MAC and PHY circuits using four conductors per up to eight ports, operating at faster rates than the external data rate, thereby reducing the number of pins and improving system layout and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a traditional Media Independent Interface (MII) with 24 ports operating at 10/100 Mbps is used, then the interface can support multiple ports, but the number of pins required is 384, increasing production cost and device complexity

Engineering Contradiction:
Improveport densityVSAvoidnumber of pins
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple parallel data paths into a single serial data path by integrating a serializer that multiplexes data from multiple ports onto one conductive path. This merging of multiple channels into one reduces the number of required pins while maintaining support for multiple ports, directly resolving the contradiction between port density and device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces the mechanical/electrical parallel connection system with a serial communication system. Instead of using multiple separate conductors for each port (parallel mechanism), the invention uses a serial data path where data from multiple ports is time-multiplexed over a single conductor, significantly reducing pin count while maintaining functionality

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If the number of conductors is reduced from 384 pins to fewer pins using serial interfaces, then production cost and device complexity are reduced, but the data transmission rate per conductor must increase

Engineering Contradiction:
Improvenumber of pinsVSAvoiddata transmission rate
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent implements periodic action through time-division multiplexing, where data from different ports is transmitted in sequential time slots over the same serial conductor. The serializer periodically switches between different port data streams, allowing multiple ports to share a single high-speed serial path, thus reducing pin count while achieving the required aggregate data transmission rate

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the data transmission parameters by converting from parallel low-speed transmission to serial high-speed transmission. The serializer transforms multiple slow parallel data streams into a single fast serial stream, changing the temporal and spatial distribution of data transmission. This parameter transformation allows fewer pins to handle the same or greater total bandwidth

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2577945B1Multiplexed serial media independent interface
Publication Date: 2019.12.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • EP2577945B1 patent drawingFigure 1
  • EP2577945B1 patent drawingFigure 2

AI summary

Systems, methods, and devices are provided for a multiplexed serial media independent interface (110-1, 110-N, 210). One system for handling data includes a physical layer (PHY) circuit (102-1, 102-N, 202-1, 202-N) operating at a first rate including a number of ports (104-1, 104-P), a media access control (MAC) circuit (108, 208-1, 208-N) operating at the first rate including a number of ports, and a multiplexed serial media independent interface (110-1, 110-N, 210) between the MAC circuit (108, 208-1, 208-N) and the PHY circuit (102-1, 102-N, 202-1, 202-N) operating at a second rate, which is greater than the first rate. The interface (110-1, 110-N, 210) includes a number of conductors and is configured to communicate data between the MAC circuit (108, 208-1, 208-N) and the PHY circuit (102-1, 102-N, 202-1, 202-N) via four conductors per up to eight ports (104-1, 104-P) of the PHY circuit (102-1, 102-N, 202-1, 202-N).