Differential Multiplexer Biasing for High-Voltage Clock Tolerance

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Solution Overview

Problem

In high-speed communication protocols, such as PCI-Express, the amplitude of the reference clock signal can exceed the junction breakdown voltage of transistors, leading to transistor degradation due to gate oxide breakdown and process parameter shifts, necessitating a solution to maintain junction voltages below breakdown voltages.

Innovation Solution

A differential multiplexer design that maintains transistors in weak conductive states through DC biasing and AC coupling, using bandgap circuits and current sources to keep gate terminals at nearly half the voltage swing of the input signal, preventing high voltages from exceeding transistor junctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the multiplexer is designed to handle high-speed communication protocols with large voltage swings, then the signal transmission capability is improved, but the transistor junction voltages may exceed breakdown voltages causing degradation

Engineering Contradiction:
Improvesignal transmission capabilityVSAvoidtransistor junction voltage tolerance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces an intermediary voltage reference system consisting of a first voltage reference circuit and a second voltage reference circuit that generate scaled reference voltages. These intermediary voltage levels act as mediators between the high-voltage input signals and the transistor junctions, ensuring that transistor gate voltages never exceed breakdown thresholds while still allowing the multiplexer to handle high-speed communication protocols with large voltage swings.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically adjusts voltage parameters by generating multiple scaled reference voltages (first scaled reference voltage and second scaled reference voltage) from the input reference clock signal. By changing voltage levels according to the selected input channel, the circuit maintains transistor junction voltages within safe operating ranges while accommodating different signal amplitude requirements for high-speed communication protocols.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If voltage reference circuits are added to scale down reference clock signals, then transistor protection is improved, but circuit complexity increases

Engineering Contradiction:
Improvetransistor protectionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the voltage reference functionality into multiple independent voltage reference circuits, where each circuit generates a specific scaled reference voltage for a particular input channel. This segmentation allows each voltage reference circuit to be optimized for its specific function and enables modular design, where the complexity is distributed across multiple simple, dedicated circuits rather than one complex universal circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The voltage reference circuits serve multiple functions: they generate scaled reference voltages for transistor gate control, provide protection against overvoltage conditions, and enable the multiplexer to handle different signal amplitude requirements. By making the voltage reference system multi-functional, the patent reduces the need for separate protection circuits, thereby managing overall circuit complexity while maintaining comprehensive transistor protection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12074593B1High-voltage tolerant multiplexer
Publication Date: 2024.08.27 SYNOPSYS INC
  • US12074593B1 patent drawing
  • US12074593B1 patent drawing
  • US12074593B1 patent drawing

AI summary

A differential multiplexer includes a number of input stages. Each stage includes, in part, first and second transistor receiving an input signal and the inverse of the input signal, a biasing circuit supplying a bias to the gate terminal of the first and second transistors, a current source coupled between a source terminal of the first and second transistors and a ground terminal, a first switch coupling a drain terminal of the first transistor to a first terminal of a first resistor having a second terminal coupled to a supply voltage, a second switch coupling a drain terminal of the second transistor to a first terminal of a second resistor having second terminal coupled to the supply voltage, a third switch coupling the drain terminal of the first transistor to the supply voltage, and a fourth switch coupling the drain terminal of the second transistor to the supply voltage.