Multiplexer Buffer Fan-Out Balancing for Memory Access
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Solution Overview
Problem
Existing memory access systems face increased memory access time and chip area occupancy due to uneven fan-out distribution among selector lines, leading to inefficiencies in multiplexing circuits and buffer element utilization.
Innovation Solution
The method involves organizing buffer elements in a pre-defined manner to distribute the fan-out uniformly among input selector signals, enabling each multiplexing circuit with distinct combinations of selector signals to reduce timing delays and capacitive loads, thereby minimizing the number of buffer elements and chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hierarchical multiplexer arrangement is used to select memory locations, then memory access capability is improved, but selector lines driving more multiplexers have larger critical path increasing access time
Solution Approach 1:
The patent applies dynamic buffer allocation by adjusting buffer element placement based on the specific access pattern and hierarchical level being accessed. Buffers are strategically positioned at different stages of the hierarchical multiplexer structure, allowing the system to dynamically optimize the critical path for different access scenarios rather than using a static uniform distribution.
Solution Approach 2:
The patent implements local quality optimization by placing buffer elements at specific locations within the hierarchical structure where they are most needed. Rather than uniform distribution, buffers are concentrated at critical junction points in the hierarchy where signal strength degradation would most impact access time, creating locally optimized regions within the overall structure.
2Productivity
If hierarchical multiplexer arrangement is used, then memory access capability is improved, but varying number of buffer elements at different levels increases chip area
Solution Approach 1:
The patent merges buffer elements across the hierarchical structure by sharing buffers between multiple multiplexer levels and arrays. A single buffer can serve multiple hierarchical levels simultaneously, reducing the total number of buffer elements required compared to having dedicated buffers at each level, thus reducing overall chip area while maintaining access capability.
Solution Approach 2:
The patent implements universal buffer elements that can function at multiple hierarchical levels and serve multiple arrays simultaneously. These multi-functional buffers are designed to operate effectively regardless of their position in the hierarchy, allowing the same buffer design to be reused throughout the structure and reducing the total buffer count required.
Data Source
AI summary
A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set of input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit.