Multiplexer Clock Power Isolation for DDR Signal Quality
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Solution Overview
Problem
Semiconductor devices that output data in synchronization with both edges of a clock signal, such as DDR SDRAM, face signal quality issues due to noise interaction between multiplexers and clock dividing circuits operating on the same internal power supply voltage.
Innovation Solution
The semiconductor device employs separate power supply circuits for the clock dividing circuit and multiplexer, generating internal power supply voltages that are distinct and independent, preventing noise interaction and improving signal quality by operating on different power sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the multiplexer and clock dividing circuit are operated with the same internal power supply voltage, then device complexity is reduced, but noise interaction occurs and signal quality deteriorates
Solution Approach 1:
The power supply system is segmented into separate domains: the clock dividing circuit operates on an first internal power supply voltage while the multiplexer operates on a second internal power supply voltage. This segmentation isolates noise sources and prevents interaction between the two circuits, resolving the noise quality issue while maintaining manageable complexity through modular power supply design.
2Object-affected harmful factors
If separate power supply circuits are used for clock dividing circuit and multiplexer, then noise interaction is reduced and signal quality improves, but device complexity increases
Solution Approach 1:
Power supply isolation circuits serve as intermediaries between the first and second internal power supply voltages. These intermediary circuits enable independent voltage regulation and noise isolation for each functional block (clock dividing circuit and multiplexer), achieving noise reduction while managing complexity through dedicated power supply interface structures.
Data Source
AI summary
A semiconductor device includes: a DLL circuit that generates an internal clock signal based on an external clock signal; a clock dividing circuit that generates two complementary internal clock signals having different phases based on the internal clock signal; and a multiplexer that outputs two internal data signals in synchronization with the two clock signals based on internal data signals, respectively. An internal power supply voltage supplied to the clock dividing circuit and an internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device. This prevents interaction among noises.