Multiplexer D Flip-Flop Circuit for Lower Scan Logic Overhead
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Solution Overview
Problem
Existing scan D flip-flops in chips require separate combinatorial and timing logic units, leading to increased area, power consumption, and cost, which is problematic for applications sensitive to Performance, Power, and Area (PPA) metrics.
Innovation Solution
A D flip-flop with integrated multiplexer function, utilizing transmission gates and an inverted latch unit, where clock signals control the gates' operation to combine register and multiplexer functions, reducing the need for separate units and minimizing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate combinatorial and timing logic units are used in scan D flip-flops, then testability is improved, but area and power consumption increase
Solution Approach 1:
The patent combines the multiplexer function (combinatorial logic) and the D flip-flop function (timing logic) into a single integrated unit. The transmission gates are controlled by clock signals to perform both data selection and clocked storage operations, eliminating the need for separate combinatorial and timing logic units while maintaining testability through the scan interface.
Solution Approach 2:
The transmission gates serve multiple functions: they act as multiplexers for data selection and simultaneously function as clocked switches for the flip-flop operation. The same hardware structure supports both normal operational mode and scan test mode, providing universal functionality that reduces overall circuit complexity and area.
2Reliability
If separate combinatorial and timing logic units are used in scan D flip-flops, then testability is improved, but power consumption increases
Solution Approach 1:
By merging the multiplexer and flip-flop into a single integrated structure, the patent reduces the total number of logic units and interconnections, thereby reducing static and dynamic power consumption. The unified design eliminates redundant switching operations and reduces leakage current from separate control logic.
Solution Approach 2:
The multi-functional transmission gates reduce power consumption by eliminating the need for separate control logic for multiplexing and clocking operations. A single set of control signals manages both functions, reducing the overall switching activity and associated dynamic power consumption across the circuit.
3Adaptability or versatility
If separate combinatorial and timing logic units are used in scan D flip-flops, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges the multiplexer control logic and flip-flop clocking logic into a unified transmission gate structure controlled by clock signals. This integration simplifies the overall hardware architecture by reducing the number of discrete logic units, interconnections, and control signal paths while maintaining full functionality for both operational and test modes.
Data Source
AI summary
The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.