Multibit Multiplexer Flip-Flop Circuit With Testable Pass-Gate Input
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-performance flip-flop circuits with multiplexers face issues of delayed logic on critical paths and stuck-at fault visibility, particularly in the Texas Instruments TMS320C6400 family of digital signal processors, leading to suboptimal frequency performance and reduced stuck-at-fault coverage.
Innovation Solution
A multibit combined multiplexer and flip-flop circuit design with a single layer of pass gates, controlled by clocked signal pairs, and an integrated test input for enhanced fault visibility, reducing setup time and power consumption while improving stuck-at-fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multiplexer is built into the flip-flop input, then frequency performance is improved by approximately 5%, but stuck-at-fault coverage is reduced because test pins become unobservable
Solution Approach 1:
The circuit is segmented into normal operation mode and test mode, allowing different functionalities to be activated separately. During normal operation, the multiplexer functions as intended for frequency improvement, while during test mode, the scan path is activated to restore observability for fault coverage
Solution Approach 2:
The flip-flop circuit is designed to perform multiple functions: it operates as a standard multiplexer-flip-flop combination during normal operation to improve frequency performance, and simultaneously provides scan path functionality during test mode to maintain stuck-at-fault coverage, making it a multi-functional circuit
2Adaptability or versatility
If multiple layers of pass gates are used in the multiplexer input, then input selection flexibility is improved, but setup time and power consumption increase
Solution Approach 1:
The test input functionality is extracted as a separate, dedicated input terminal that bypasses the multiplexer pass gate structure. This allows the main multiplexer to use fewer pass gate layers for normal operation, reducing setup time and power consumption while the extracted test input provides the necessary flexibility for testing
Solution Approach 2:
The test input is prepared and isolated from the main signal path, allowing it to be activated preliminarily when needed for testing. This preliminary preparation enables the main circuit to operate with optimized pass gate configuration for reduced setup time, while test functionality remains available when required
Data Source
AI summary
A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.