Multiplexer Partitioning Across FPGAs With Reduced Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for partitioning large multiplexers across multiple integrated circuits face challenges due to excessive interconnect usage and complex decomposition, especially when dealing with large numbers of inputs and decoding logic, which complicates the process of distributing inputs across multiple FPGAs.
Innovation Solution
The method involves converting a multiplexer representation into a partition-neutral form, such as using tristate drivers or wired OR/AND arrays, allowing for simultaneous decomposition and partitioning across multiple integrated circuits or portions of the same circuit, reducing wire count and simplifying the distribution of inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional decomposition methods are used to partition large multiplexers across multiple integrated circuits, then the multiplexer can be distributed across FPGAs, but the interconnect usage increases significantly and the decomposition becomes complex
Solution Approach 1:
The patent applies segmentation by dividing the large multiplexer into smaller sub-multiplexers that can be independently placed on different FPGAs. The decomposition process automatically partitions the multiplexer based on available resources, breaking down the complex single-unit multiplexer into manageable segments without requiring manual intervention or complex decomposition logic.
Solution Approach 2:
The patent introduces an intermediary decomposition process that acts as a mediator between the original multiplexer design and the final partitioned implementation. This intermediary step automatically generates the partitioning scheme, eliminating the need for designers to manually handle complex decomposition and interconnect optimization.
2Adaptability or versatility
If traditional decomposition methods are used to partition large multiplexers, then the multiplexer can be distributed across multiple FPGAs, but the interconnect usage between partitions increases
Solution Approach 1:
The patent changes the parameters of the decomposition process by automatically adjusting how the multiplexer is partitioned based on FPGA resource availability and interconnect constraints. The system dynamically modifies the decomposition parameters to minimize interconnect usage while maintaining the required distribution across multiple FPGAs, rather than using fixed decomposition methods.
3Ease of manufacture
If manual partitioning methods are used for large multiplexers with many inputs, then design control is maintained, but the partitioning process becomes difficult and time-consuming
Solution Approach 1:
The patent implements self-service by enabling the decomposition process to automatically perform partitioning without requiring manual designer intervention. The system serves itself by taking the multiplexer design as input and automatically generating the partitioned implementation, eliminating the time-consuming manual partitioning process while maintaining design integrity.
Solution Approach 2:
The patent applies preliminary action by performing the decomposition and partitioning steps automatically during the design synthesis phase, before the actual FPGA implementation. This preliminary automated partitioning prepares the design for efficient implementation across multiple FPGAs, saving significant time during the manufacturing and deployment phases.
Data Source
AI summary
Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second multiplexers. Another exemplary method includes decomposing a representation of a first multiplexer into a representation of a plurality of second multiplexers, which are coupled together at a common output without any intervening multiplexers between the second multiplexers and the common output, and partitioning the second multiplexers between portions of at least one integrated circuit.