Multiplexer-Gated VCO Circuit for Low-Jitter Clock Recovery

Solution Overview

Problem

Traditional gated voltage-controlled oscillators in clock and data recovery circuits suffer from unnecessary jitter in the output clock signal due to asymmetry in NAND gate circuits, which can be mitigated by increasing bandwidth but at the cost of increased operating current and circuit area.

Innovation Solution

Replacing the NAND gate with a multiplexer in the gated voltage-controlled oscillator, coupled with a delay unit, to improve symmetry and reduce jitter, where the multiplexer selectively outputs signals based on the gating signal, allowing for better phase realignment and reduced circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bandwidth of the NAND gate is increased to reduce jitter, then the jitter is reduced, but the operating current increases and the circuit area is enlarged

Engineering Contradiction:

Improvejitter reductionVSAvoidoperating current

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the fundamental parameter of the circuit topology by replacing the NAND gate with a multiplexer-based structure. This structural parameter change enables achieving the same jitter reduction function without requiring increased bandwidth, thus avoiding the associated increase in operating current and circuit area.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the traditional NAND gate-based GVCO mechanism with a multiplexer-based mechanism. This substitution allows for better symmetry control and jitter reduction without relying on increasing the bandwidth of the original NAND gate structure, thereby avoiding the penalty of increased current consumption and area.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If the bandwidth of the NAND gate is increased to reduce jitter, then the jitter is reduced, but the circuit area is enlarged

Engineering Contradiction:

Improvejitter reductionVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the fundamental parameter of the circuit topology by replacing the NAND gate with a multiplexer-based structure. This structural parameter change enables achieving the same jitter reduction function without requiring increased bandwidth, thus avoiding the associated increase in circuit area.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the traditional NAND gate-based GVCO mechanism with a multiplexer-based mechanism. This substitution allows for better symmetry control and jitter reduction without relying on increasing the bandwidth of the original NAND gate structure, thereby avoiding the penalty of increased area.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If the NAND gate is used to constitute the GVCO, then the circuit structure is simple, but asymmetry causes unnecessary jitter

Engineering Contradiction:

Improvecircuit structureVSAvoidsignal jitter

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent substitutes the asymmetric NAND gate structure with a symmetric multiplexer-based structure. This substitution maintains relative simplicity while fundamentally improving symmetry, thereby eliminating the jitter caused by NAND gate asymmetry.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent addresses the asymmetry problem by using a multiplexer structure that provides better symmetry compared to the inherently asymmetric NAND gate. The multiplexer allows for more balanced signal paths, reducing the asymmetry-induced jitter while maintaining circuit simplicity.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS8952760B2Gated voltage-controlled oscillator and clock and data recovery circuit

Publication Date: 2015.02.10 GLOBAL UNICHIP CORPORATION

AI summary

A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.