Multiplexer Output Latching for Glitch-Free Low-Power Logic
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Solution Overview
Problem
Conventional sequential circuitry experiences power dissipation issues due to glitches in multiplexer outputs, which change multiple times before settling, leading to unnecessary charging and discharging of nodes in combinational logic.
Innovation Solution
A storage element is inserted to sample the signal after it has stabilized, using a 'ready' signal with a delay matching the circuitry's delay to prevent the output from changing until the final value is achieved, thereby reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential circuitry uses combinational logic with synchronous registers, then the circuit can process data, but the output signal changes multiple times before settling causing glitches and power dissipation
Solution Approach 1:
The patent applies preliminary action by delaying the clock signal to ensure all combinational logic paths have completed their transitions before the register samples the output. This preliminary timing adjustment prevents glitches from propagating to the register, eliminating unnecessary power dissipation while maintaining data processing capability.
Solution Approach 2:
The patent introduces a delayed clock signal as an intermediary between the combinational logic and the register. This intermediary ensures that the register only samples the output after all glitch-prone transitions have settled, thereby preventing power dissipation caused by glitch propagation while preserving the data processing function.
2Speed
If the multiplexer output is allowed to change freely in response to data and select inputs, then the circuit responds dynamically, but the output changes several times before settling creating glitches
Solution Approach 1:
The patent uses preliminary action by delaying the clock signal to anticipate when the multiplexer output will settle. This allows the register to sample the stable final value without capturing intermediate glitch states, thus maintaining signal stability while preserving the dynamic response capability of the multiplexer.
Solution Approach 2:
The patent implements feedback by using the delayed clock signal to control register sampling based on the actual settling time of the multiplexer output. This feedback mechanism ensures that the register only captures stable values, improving signal reliability while maintaining the multiplexer's dynamic response to input changes.
3Adaptability or versatility
If additional combinational logic receives the multiplexer output, then the circuit functionality is extended, but nodes are charged and discharged multiple times dissipating power
Solution Approach 1:
The patent applies preliminary action by ensuring the register samples the multiplexer output only after all transitions have completed. This preliminary timing control prevents glitch propagation to additional combinational logic, reducing power consumption while maintaining extended circuit functionality.
Solution Approach 2:
The patent introduces a delayed clock signal as an intermediary that controls when additional combinational logic receives valid data. This intermediary prevents unnecessary node charging and discharging in downstream logic, reducing power consumption while preserving the versatility of the extended circuit functionality.
Data Source
AI summary
When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.