Time Domain Multiplexer Inter-Symbol Interference Reduction
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Solution Overview
Problem
Conventional high-speed time domain multiplexers experience inter-symbol interference, particularly inter-channel interference, during clock transitions, leading to timing jitter in the output bit stream due to variability in voltage crossing points.
Innovation Solution
The implementation of return-to-differential-zero latches and pre-selectors in high-speed time domain multiplexers, which sample bit streams at specific clock polarities and drive inputs to a neutral state when not selected, reducing inter-symbol interference by eliminating pattern dependency and ensuring the output is solely based on the selected bit stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional time domain multiplexers are used to achieve high-speed data transmission, then transmission rate is improved, but inter-symbol interference increases causing timing jitter
Solution Approach 1:
The patent applies preliminary action by driving the output to a neutral state (differential zero) before the selection switch changes states. This pre-action ensures that when the switch transitions between input signals, the output starts from a known neutral reference point, preventing inter-symbol interference and timing jitter while maintaining high-speed operation
2Productivity
If conventional multiplexers sample both bit streams continuously, then data throughput is maintained, but inter-channel interference occurs during clock transitions
Solution Approach 1:
The patent extracts the harmful interference component by implementing a selection switch that isolates the output to only the currently selected input bit stream. During clock transitions, the switch effectively removes the unselected bit stream from the output path, eliminating inter-channel interference while maintaining continuous data throughput through proper timing control
3Reliability
If the output voltage depends on both present and previous bit states, then data integrity is maintained, but voltage variability causes crossing point shifts
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the output voltage parameter to a neutral state (differential zero) during transitions between bit stream selections. This parameter change decouples the output from dependence on previous bit states, stabilizing the crossing points while maintaining data integrity through controlled voltage transitions
Data Source
AI summary
Method and system for a high-speed multiplexer with reduced inter-symbol interference are disclosed. In one embodiment of the present invention, two input bit streams are interleaved by a multiplexer to derive an output bit stream. Each input bit stream is latched by a return-to-differential-zero latch that drives its input bit stream to a neutral state when it is not selected by the multiplexer as output. In an alternate embodiment of the present invention, a pre-selector receives two input signals, determines which of the two input signals will be selected as output of the multiplexer and passes the bit stream unaltered, while passing a differential zero value in place of the unselected input bit stream.