Multiplexer-Based Latch Control for Random Resistant Logic Testability
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Solution Overview
Problem
Current integrated circuit (IC) testing methods face challenges in achieving effective test controllability and observability of random resistant logic, particularly due to the impracticality of exhaustive testing and the limitations of pseudo-random testing, which results in low fault coverage and inefficient circuit excitation, often requiring additional hardware that impacts timing, power consumption, and device area.
Innovation Solution
The method involves configuring a multiplexer device within the IC design to pass signals from observation points and preexisting combinational logic to a storage latch, using preexisting nets as control points, and employing a test enable signal to selectively pass logic signals, thereby facilitating random testing without adding extra latch devices, thus minimizing design impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pseudo-random testing is used to reduce test pattern complexity, then test generation simplicity is improved, but fault coverage deteriorates due to low circuit excitation
Solution Approach 1:
The testing system is segmented into multiple independent scan chains that can be operated in parallel. Each scan chain can be independently configured and tested, allowing the overall system to achieve better fault coverage through diversified test patterns while maintaining simplicity in individual chain management
Solution Approach 2:
The scan chain configuration is made dynamic and reconfigurable. Different scan chain configurations can be selected based on the specific testing requirements, allowing the system to adapt between simple pseudo-random testing and more comprehensive deterministic testing approaches as needed
2Difficulty of detecting and measuring
If additional latches are added to improve controllability and observability of random resistant logic, then testability is improved, but device area and power consumption worsen
Solution Approach 1:
Existing scan chain latches are made multi-functional by enabling them to serve both as normal circuit storage elements and as test observation/control points. The same physical latches are used for both functional operation and testing purposes, eliminating the need for separate dedicated test latches
Solution Approach 2:
The existing scan chain infrastructure is utilized to provide test capabilities without requiring external or additional dedicated test hardware. The scan chains themselves are configured to perform both normal operation and testing functions, making the system self-sufficient for testing needs
3Difficulty of detecting and measuring
If additional latches are added to improve controllability and observability of random resistant logic, then testability is improved, but timing performance worsens
Solution Approach 1:
The scan chain latches serve dual purposes as both functional circuit elements and test control/observation points. This eliminates the need for additional dedicated test latches that would introduce extra timing delays, as the same latches are used for both purposes without adding redundant stages to the timing path
4Reliability
If exhaustive deterministic testing is used to achieve complete fault detection, then fault coverage is improved, but test pattern complexity and time consumption worsen
Solution Approach 1:
The circuit is divided into multiple scan chains that can be tested in parallel. This segmentation allows comprehensive testing of different circuit portions simultaneously, reducing the overall test time compared to sequential exhaustive testing of the entire circuit as a single unit
Solution Approach 2:
Rather than implementing complete exhaustive deterministic testing of all possible input combinations, the system uses a configured set of scan chains that provide sufficient fault coverage for critical areas. This partial action approach achieves adequate fault detection without the prohibitive time cost of complete exhaustive testing
Data Source
AI summary
A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.