Multiplexer Multiplier Computation Device for Precision Scaling
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Solution Overview
Problem
The circuit scale of an operation unit for double-precision data is about four times that of single-precision data, leading to inefficient use of circuit elements when switching between double-precision and single-precision computations, resulting in reduced computation performance without increasing the circuit scale.
Innovation Solution
A computation device with a multiplexer and multipliers that switch between different data bit lengths by dividing input data into high-order and low-order parts, allowing all multipliers to perform operations in both computation modes without increasing the circuit scale, and using adders and partial adders to combine results efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If one operation unit for double-precision data is used, then double-precision computation is achieved, but circuit element utilization is low when performing single-precision computations
Solution Approach 1:
The input data is segmented into high-order data and low-order data by the multiplexer. When double-precision computation is required, the operation unit processes two double-precision data items. When single-precision computation is required, the same operation unit processes four single-precision data items by receiving additional input data, thereby segmenting the computational tasks to fully utilize circuit elements.
Solution Approach 2:
The operation unit is designed with multi-functionality to perform both double-precision and single-precision computations using the same hardware circuit. The multiplexer configures the operation unit to accept different numbers of input data (two for double-precision, four for single-precision), making the circuit universally applicable to different computation modes without wasting circuit elements.
2Measurement precision
If the operation unit is designed for double-precision data, then high precision computation is achieved, but computation speed for single-precision data is reduced due to unused circuit elements
Solution Approach 1:
The computation device dynamically switches between double-precision and single-precision computation modes based on the computation mode signal. The multiplexer reconfigures the operation unit's input data paths dynamically, allowing the circuit to adapt its behavior to match the required computation type, thereby optimizing computation speed for the current task while maintaining support for high precision when needed.
Solution Approach 2:
The device changes operational parameters (number of input data items, data bit width) based on the computation mode. When switching from double-precision to single-precision mode, the parameter of input data quantity changes from two to four items, and the data bit width parameter is adjusted accordingly, enabling the circuit to operate at optimal speed for the current precision requirement.
3Productivity
If circuit scale is increased to improve computation performance, then more operations can be performed, but device complexity and size increase
Solution Approach 1:
Instead of increasing circuit scale by adding separate operation units for different precision levels, the invention uses a single operation unit that can universally handle both double-precision and single-precision computations. This multi-functional approach improves computation performance by ensuring full utilization of circuit elements without increasing device complexity or size.
Solution Approach 2:
The invention merges the functionality of separate double-precision and single-precision operation units into a single unified operation unit. By combining these functions and using a multiplexer to dynamically configure the input data paths, the device achieves improved computation performance without the overhead of additional circuitry.
Data Source
AI summary
A computation device includes: a data multiplexer configured to output first high-order data as first output data and fifth output data, output first low-order data as third output data and seventh output data, output second high-order data as second output data, output second low-order data as fourth output data, output third high-order data, which is high-order data having a second bit number out of third input data, as sixth output data, and output third low-order data, which is low-order data having the second bit number out of the third input data, as eighth output data when a mode signal indicates a second computation mode; and first to fourth multipliers each of which multiplies two output data.