Multiplexer Node Clock Synchronization for Delay Compensation

Solution Overview

Problem

Network environments using time division multiplexing suffer from bandwidth loss due to internal delays within nodes and transmission delays between nodes.

Innovation Solution

A method is introduced to synchronize the real-time clocks of nodes with a multiplexer and compensate for transmission delays by using a synchronization word with a real-time clock, address, and delay fields, and calculating transmission delays using the equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot to adjust the clock settings of each node.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If time division multiplexing is used to split bandwidth into channels, then multiple data streams can be combined and transmitted, but bandwidth loss occurs due to internal delays within nodes and transmission delays between nodes

Engineering Contradiction:
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by calculating and compensating for transmission delays in advance. Each node pre-calculates its delay value based on the equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot and adjusts its clock setting before data transmission occurs. This advance compensation ensures that data from multiple nodes arrives simultaneously at the multiplexer without wasting bandwidth slots, thereby resolving the contradiction between maximizing bandwidth utilization and accounting for transmission delays.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If real-time clock synchronization is implemented across all nodes, then data transmission timing can be coordinated, but system complexity increases due to the need for clock synchronization mechanisms

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling each node to autonomously calculate its own delay value and adjust its local clock without requiring complex centralized synchronization control. Each node uses the equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot to self-determine its timing compensation based on its position in the network, thereby achieving reliable data transmission timing while minimizing system complexity.

Inventive Principle:
Principle #25Self-service

3Productivity

If delay compensation is calculated using the equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot, then transmission delays can be accounted for, but computational requirements increase

Engineering Contradiction:
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by transforming the complex delay compensation problem into a modular arithmetic equation. By changing the approach from continuous time adjustment to discrete modular arithmetic using the equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot, the system achieves accurate delay compensation with simplified computational requirements. The parameters M (number of time slots) and Tslot (duration of each time slot) are pre-defined, making the calculation efficient and scalable.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7447238B2Method for compensating for internal delays within each node and transmission delays between the nodes
Publication Date: 2008.11.04
  • US7447238B2 patent drawing
  • US7447238B2 patent drawing
  • US7447238B2 patent drawing

AI summary

A method for compensating for one or more transmission delays between a multiplexer, a first node and a second node. In one embodiment, the method includes synchronizing a first real time clock of the multiplexer as the real time clock of the first node and as the real time clock of the second node; receiving data from the first node; calculating a transmission delay between the multiplexer and the first node using an equation (RTCK+DelayK)mod(M·Tslot)=(K−1)·Tslot, where M refers to the number of time slots within a bandwidth of a medium configured for communicating data between the multiplexer, the first node and the second node, Tslot refers to the duration of each time slot, K refers to a node address, mod refers to a modulo operation, RTCK refers to the real time clock of the Kth node and DelayK refers to accumulated transmission delay from the multiplexer to the Kth node; sending a second real time clock of the multiplexer, a first number and the transmission delay to the first node; and setting the real time clock of the first node to be equal to the second real time clock of the multiplexer plus the transmission delay.