Multiplexer Routing Network Layout for Low-Delay FPGA Interconnects
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Solution Overview
Problem
Existing interconnection networks in FPGAs are not well-suited due to high size and delay costs, and have not kept pace with the evolving technology, making them inefficient for FPGA designs.
Innovation Solution
A multiplexer-based non-blocking routing network is implemented, using a single level of multiplexers in each row to calculate signal routing costs, providing routing equivalence to crossbar networks and reducing signal propagation time by using wide multiplexers that bypass multiple switching components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-stage crossbar networks are used, then routing equivalence and non-blocking functionality are achieved, but device size and delay costs increase
Solution Approach 1:
The network is divided into multiple rows, each independently equipped with multiplexers. This segmentation allows each row to handle routing independently, eliminating the need for complex multi-stage crossbar structures while maintaining non-blocking routing functionality.
Solution Approach 2:
Instead of using physical multi-stage crossbar switches, the patent uses numerical values (bit patterns) to represent and copy routing states. The number of bit differences between source and destination row values directly indicates the number of multiplexer stages required, enabling virtual routing without physical complexity.
2Reliability
If traditional multi-stage crossbar networks are used, then routing equivalence and non-blocking functionality are achieved, but signal propagation delay increases
Solution Approach 1:
The routing path is segmented into individual row transitions, where each transition corresponds to a single multiplexer stage. This reduces the total number of switching components a signal must traverse compared to traditional multi-stage networks, thereby reducing propagation delay.
Solution Approach 2:
Numerical values are pre-assigned to each row to encode routing information. The routing cost (number of bit differences) is calculated in advance, allowing the system to select optimal paths that minimize propagation delay before signals are actually routed.
3Device complexity
If a multiplexer-based network is used, then device size and delay are reduced, but the complexity of calculating optimal routing paths increases
Solution Approach 1:
Routing information is copied into numerical values assigned to each row. The routing cost between any two rows is calculated by counting the number of differing bits between their numerical values, which is a simple and efficient operation compared to analyzing complex physical routing paths.
Solution Approach 2:
The patent transforms the routing problem from a spatial/physical domain into a numerical/bit-domain problem. By representing rows as numerical values, the complex task of finding optimal paths becomes a simple matter of comparing bit patterns and counting differences, significantly reducing calculation complexity.
Data Source
AI summary
A computer-implemented method is described for determining cost in a non-blocking routing network that provides routing functionality using a single level of a plurality of multiplexers in each row of the routing network. The method includes assigning a respective numerical value, represented by bits, to each row of the routing network. A number of bits that differ between the respective numerical values of each pair of rows of the routing network indicates a number of row traversals necessary to traverse from a first row of the pair to a second row of the pair. A signal routing cost is computed from the number of bits that differ between the respective numerical values of the first row and the second row of the routing network. The calculated signal routing cost is provided to a placement module.