Multiplexing Data Buffer Circuitry for Memory Training
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Solution Overview
Problem
Existing memory circuitry training methods fail to effectively determine equalization parameters for cyclic redundancy check (CRC) circuitry due to its lack of access to memory devices, leading to errors in signal transmission between memory controllers and circuitries.
Innovation Solution
Incorporating multiplexing data buffer circuitry that couples the CRC circuitry to memory devices via selection circuitry, allowing training data to be written and read from memory devices to determine equalization parameters for CRC circuitry and corresponding interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CRC circuitry is excluded from direct memory device access, then device complexity is reduced, but measurement precision of equalization parameters deteriorates
Solution Approach 1:
A multiplexer is introduced as an intermediary component that enables the CRC circuitry to access memory devices indirectly. The multiplexer selectively connects the CRC circuitry to memory devices during training operations, allowing equalization parameters to be measured with high precision while maintaining a simplified circuitry structure where the CRC circuitry does not require direct permanent access to memory devices.
2Measurement precision
If CRC circuitry is coupled directly to memory devices, then measurement precision of equalization parameters is improved, but device complexity increases
Solution Approach 1:
The multiplexer serves multiple functions: it acts as a signal router during normal operations and as a connection intermediary during training operations. This multi-functionality allows the CRC circuitry to access memory devices when needed for training without requiring a permanent direct connection, thereby improving measurement precision of equalization parameters while avoiding the need for a complex dedicated connection structure.
3Measurement precision
If training data is written and read through multiplexing data buffer circuitry, then equalization parameters accuracy is improved, but loss of time increases
Solution Approach 1:
The system performs training operations during idle periods or initialization phases before normal data processing begins. By conducting the write and read operations through the multiplexing data buffer circuitry during these preliminary training phases, the system obtains accurate equalization parameters without interfering with or extending the time required for normal operational data processing.
Data Source
AI summary
A memory system includes a memory controller and memory circuitry. The memory controller outputs a first training signal. The memory circuitry is coupled to the memory controller. The memory circuitry includes a memory device and multiplexing data buffer circuitry. The multiplexing data buffer circuitry is coupled to the memory device. The multiplexing data buffer circuitry includes first circuitry and second circuitry. The second circuitry is coupled to the memory device. The second circuitry receives the first training signal from memory controller comprising first training data associated with the first circuitry, writes the first training data to the memory device, and read the written first training data from the memory device, and outputs the written first training data to the memory controller. The memory controller is configured to determine equalization parameters for the first circuitry based on the written first training data.