Multiplexing Inputs and Delayed Signals for Circuit Emulation Debugging
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Solution Overview
Problem
Complex integrated circuit designs face verification challenges due to advancing processing technology and increasing complexity, making it difficult to debug and simulate errors effectively using traditional tools, especially with intermittent errors that are hard to reproduce.
Innovation Solution
A method involving logic replication, snapshot solutions, and time division multiplexer techniques to capture initial condition signals and input signals before an error occurs, allowing for detailed simulation and debugging by replicating logic circuits, storing snapshots of design registers, and time-multiplexing data to recreate error conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional simulation tools are used to verify complex circuit designs, then verification coverage is limited, but debugging efficiency and error detection capability deteriorate
Solution Approach 1:
The patent creates a replicated copy of the design logic circuit in the emulation system. This replica allows the system to capture and store initial condition signals and input signals that lead up to an error state. By copying the logic structure, the system can replay the exact sequence of events that caused an error, enabling both comprehensive verification coverage and efficient debugging by allowing designers to step through and examine the captured signal sequences.
2Ease of operation
If logic replication is implemented to capture initial condition signals, then debugging capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential signals needed for debugging - specifically the initial condition signals and input signals - from the full circuit operation. Rather than replicating or monitoring the entire circuit, the system captures these specific signal sequences and stores them for later analysis. This extraction approach provides powerful debugging capability while minimizing the additional complexity introduced by the capture mechanism.
Solution Approach 2:
The patent introduces a signal capture and storage mechanism that acts as an intermediary between the design logic and the debugging interface. This intermediary component captures the relevant signal sequences, stores them in memory, and makes them available for analysis without requiring direct modification of the core logic or complex real-time monitoring of the entire circuit.
3Adaptability or versatility
If time division multiplexing is used to route signals through cross point switch, then resource utilization is improved, but signal routing complexity increases
Solution Approach 1:
The patent implements time division multiplexing where signals are routed through the cross-point switch in periodic time slots. During capture mode, the switch routes signals to capture memory; during analysis mode, it routes the same physical resources to the analysis interface. This periodic switching of signal paths allows the system to use the same hardware resources for multiple functions at different times, improving resource utilization while the control logic manages the switching complexity.
Data Source
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AI summary
Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.