Multiplexing Embedded Clock Signals with Jitter Attenuation
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Solution Overview
Problem
Existing data transmission systems face challenges in multiplexing and demultiplexing signals from different synchronization sources with high phase accuracy, particularly when these signals have slight frequency deviations, failing to meet the wander requirements of telecom standards like ITU-T G.813.
Innovation Solution
A data transmission system with a clock extraction module, sampling module, and multiplexing module at the first node, and a demultiplexing module with jitter attenuating means and interface module at the second node, which samples and stabilizes clock signals to ensure high timing accuracy and reduce frequency jitter below predefined levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data signals from different synchronization sources are multiplexed together, then transmission efficiency is improved, but phase accuracy and timing precision deteriorate due to frequency deviations between sources
Solution Approach 1:
The patent segments the multiplexed signal processing into separate handling paths for different synchronization sources. Each source's clock signal is extracted and processed independently through dedicated jitter attenuating means, preventing the mixing of frequency deviations while maintaining efficient multiplexed transmission of multiple data signals.
Solution Approach 2:
The patent introduces an intermediary clock extraction and stabilization mechanism between the multiplexed data signals and the demultiplexing process. By extracting clock signals from the multiplexed stream and passing them through jitter attenuating means before using them to control demultiplexing, the system mediates the frequency deviations to maintain phase accuracy.
2Device complexity
If clock signals with slight frequency deviations are transmitted through a common medium, then device complexity is reduced, but synchronization quality and timing precision worsen
Solution Approach 1:
The patent merges multiple clock signal handling paths into a unified processing framework. Different synchronization sources are processed through the same multiplexing and demultiplexing infrastructure, with jitter attenuation applied to each source's clock signal, reducing overall device complexity while maintaining synchronization quality.
Solution Approach 2:
The patent applies parameter changes by adjusting the clock signals through jitter attenuating means that modify the frequency and phase characteristics. This changes the parameters of the clock signals to eliminate frequency deviations while maintaining the underlying synchronization structure, improving reliability without increasing complexity.
3Adaptability or versatility
If demultiplexing is performed on multiplexed signals from different clock sources, then transmission versatility is improved, but wander and frequency jitter increase beyond telecom standards
Solution Approach 1:
The patent applies preliminary action by attenuating jitter and stabilizing clock signals before the demultiplexing operation. The jitter attenuating means processes each source's clock signal in advance, removing frequency deviations and wander before these signals are used to control the demultiplexing process, ensuring compliance with telecom standards.
Solution Approach 2:
The patent implements feedback mechanisms where the extracted clock signals are monitored for jitter and frequency deviations, and the jitter attenuating means adjusts the clock signals based on this feedback. This closed-loop control ensures that wander and frequency jitter remain within acceptable limits while maintaining transmission versatility.
Data Source
AI summary
In a data transmission system, a first node receives at least two sets of input data signals including at least two signals being based on different synchronization sources. The first node extracts a respective clock signal representing the embedded clock signals from the sources, samples and formats these signals for transmission according to a TDM structure. The TDM formatted signals are transmitted as at least one bit stream over a transmission medium to at least one second node, where the bit stream is demultiplexed into at least two sets of output data signals respective demultiplexed clock signals representing the sampled clock signals. A jitter attenuating mechanism reduces an amount of frequency jitter to below a predefined level to produce a respective clock signal having a synchronization quality superior to that of the demultiplexed clock signals. An interface module recombines each data signal with its associated clock signal.